參數(shù)資料
型號： PSD854F2A-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
封裝： ROHS COMPLIANT, TQFP-64
文件頁數(shù)： 55/128頁
文件大?。?/td> 1045K
代理商： PSD854F2A-90UT
Instructions
PSD8XXFX
Doc ID 7833 Rev 7
7.7
Data Polling flag (DQ7)
When erasing or programming in Flash memory, the Data Polling flag bit (DQ7) outputs the
complement of the bit being entered for programming/writing on the DQ7 Bit. Once the
Program instruction or the WRITE operation is completed, the true logic value is read on the
Data Polling flag bit (DQ7, in a READ operation).
●
Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after
the sixth WRITE pulse (for an Erase instruction). It must be performed at the address
being programmed or at an address within the Flash memory sector being erased.
●
During an Erase cycle, the Data Polling flag bit (DQ7) outputs a ’0.’ After completion of
the cycle, the Data Polling flag bit (DQ7) outputs the last bit programmed (it is a '1' after
erasing).
●
If the byte to be programmed is in a protected Flash memory sector, the instruction is
ignored.
●
If all the Flash memory sectors to be erased are protected, the Data Polling flag bit
(DQ7) is reset to '0' for about 100s, and then returns to the previous addressed byte.
No erasure is performed.
7.8
Toggle flag (DQ6)
The PSD offers another way for determining when the Flash memory Program cycle is
completed. During the internal WRITE operation and when either the FS0-FS7 or
CSBOOT0-CSBOOT3 is true, the Toggle flag bit (DQ6) toggles from '0' to '1' and '1' to '0' on
subsequent attempts to read any byte of the memory.
When the internal cycle is complete, the toggling stops and the data read on the data bus
D0-D7 is the addressed memory byte. The device is now accessible for a new READ or
WRITE operation. The cycle is finished when two successive READs yield the same output
data.
●
The Toggle flag bit (DQ6) is effective after the fourth WRITE pulse (for a Program
instruction) or after the sixth WRITE pulse (for an Erase instruction).
●
If the byte to be programmed belongs to a protected Flash memory sector, the
instruction is ignored.
●
If all the Flash memory sectors selected for erasure are protected, the Toggle flag bit
(DQ6) toggles to '0' for about 100s and then returns to the previous addressed byte.
Table 11.
Status bits(1)(2)(3)
Functional
block
FS0-
FS7/CSBOOT0-
CSBOOT3
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Flash memory
VIH
Data
Polling
Toggle
flag
Error
flag
X
Erase
timeout
XX
X
1.
X = Not guaranteed value, can be read either '1' or ’0.’
2.
DQ7-DQ0 represent the data bus bits, D7-D0.
3.
FS0-FS7 and CSBOOT0-CSBOOT3 are active high.
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
PSD854F2V-12JI 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-12MI 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90J 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90M 功能描述:CPLD - 復雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD-8M-01 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC
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