參數(shù)資料
型號： PSD854F2A-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
封裝： ROHS COMPLIANT, TQFP-64
文件頁數(shù)： 111/128頁
文件大?。?/td> 1045K
代理商： PSD854F2A-90UT
PSD8XXFX
Power management
Doc ID 7833 Rev 7
Bit 4
PLD Array clk
0 =
on
CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo Bit is ’0.’
1 =
off
CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
Bit 5
PLD MCell clk
0 =
on
CLKIN (PD1) input to the PLD macrocells is connected.
1 =
off
CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
1.
The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the
registers.
Table 32.
Power Management mode registers PMMR2(1)
Bit
Name
Description
Bit 0
X
0
Not used, and should be set to zero.
Bit 1
X
0
Not used, and should be set to zero.
Bit 2
PLD Array
CNTL0
0 = on
Cntl0 input to the PLD AND Array is connected.
1 = off
Cntl0 input to PLD AND Array is disconnected, saving power.
Bit 3
PLD Array
CNTL1
0 = on
Cntl1 input to the PLD AND Array is connected.
1 = off
Cntl1 input to PLD AND Array is disconnected, saving power.
Bit 4
PLD Array
CNTL2
0 = on
Cntl2 input to the PLD AND Array is connected.
1 = off
Cntl2 input to PLD AND Array is disconnected, saving power.
Bit 5
PLD Array
ALE
0 = on
ALE input to the PLD AND Array is connected.
1 = off
ALE input to PLD AND Array is disconnected, saving power.
Bit 6
PLD Array
DBE
0 = on
DBE input to the PLD AND Array is connected.
1 = off
DBE input to PLD AND Array is disconnected, saving power.
Bit 7
X
0
Not used, and should be set to zero.
1.
The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the
registers.
Table 31.
Power Management mode registers PMMR0(1) (continued)
Bit
Name
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD854F2V-12JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-12MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD-8M-01 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC
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