參數(shù)資料
型號： PSD854F2A-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
封裝： ROHS COMPLIANT, TQFP-64
文件頁數(shù)： 64/128頁
文件大?。?/td> 1045K
代理商： PSD854F2A-90UT
Specific features
PSD8XXFX
Doc ID 7833 Rev 7
10
Specific features
10.1
Flash Memory Sector Protect
Each primary and secondary Flash memory sector can be separately protected against
Program and Erase cycles. Sector Protection provides additional data security because it
disables all program or erase cycles. This mode can be activated through the JTAG port or a
device programmer.
Sector protection can be selected for each sector using the PSDsoft Express Configuration
program. This automatically protects selected sectors when the device is programmed
through the JTAG port or a device programmer. Flash memory sectors can be unprotected
to allow updating of their contents using the JTAG port or a device programmer. The MCU
can read (but cannot change) the sector protection bits.
Any attempt to program or erase a protected Flash memory sector is ignored by the device.
The Verify operation results in a READ of the protected data. This allows a guarantee of the
retention of the Protection status.
The sector protection status can be read by the MCU through the Flash memory protection
and PSD/EE protection registers (in the CSIOP block). See Table 12 and Table 13.
10.2
Reset Flash
The Reset Flash instruction consists of one WRITE cycle (see Table 10). It can also be
optionally preceded by the standard two WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after:
●
Reading the Flash Protection Status or Flash ID
●
An Error condition has occurred (and the device has set the Error flag bit (DQ5) to '1')
during a Flash memory program or erase cycle.
On the PSD813F2/3/4/5, the Reset Flash instruction puts the Flash memory back into
normal READ mode. It may take the Flash memory up to a few milliseconds to complete the
Reset cycle. The Reset Flash instruction is ignored when it is issued during a Program or
Bulk Erase cycle of the Flash memory. The Reset Flash instruction aborts any on-going
Sector Erase cycle, and returns the Flash memory to the normal READ mode within a few
milliseconds.
On the PSD83xF2 or PSD85xF2, the Reset Flash instruction puts the Flash memory back
into normal READ mode. If an Error condition has occurred (and the device has set the
Error flag bit (DQ5) to '1') the Flash memory is put back into normal READ mode within 25
μs
of the Reset Flash instruction having been issued. The Reset Flash instruction is ignored
when it is issued during a Program or Bulk Erase cycle of the Flash memory. The Reset
Flash instruction aborts any on-going Sector Erase cycle, and returns the Flash memory to
the normal READ mode within 25
μs.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD854F2V-12JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-12MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD-8M-01 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC
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