參數(shù)資料
型號(hào): PSD834F2VA-15MI
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝: PLASTIC, QFP-52
文件頁數(shù): 66/110頁
文件大?。?/td> 837K
代理商: PSD834F2VA-15MI
59/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Port C – Functionality and Structure
Port C can be configured to perform one or more
of the following functions (see Figure 29):
MCU I/O Mode
CPLD Output – McellBC7-McellBC0 outputs
can be connected to Port B or Port C.
CPLD Input – via the Input Macrocells (IMC)
Address In – Additional high address inputs
using the Input Macrocells (IMC).
In-System Programming (ISP) – JTAG port
can be enabled for programming/erase of the
PSD device. (See the section entitled
more information on JTAG programming.)
Open Drain – Port C pins can be configured in
Open Drain Mode
Battery Backup features – PC2 can be
configured for a battery input supply, Voltage
Stand-by (VSTBY).
PC4 can be configured as a Battery-on Indicator
(VBATON), indicating when VCC is less than
VBAT.
Port C does not support Address Out mode, and
therefore no Control Register is required.
Pin PC7 may be configured as the DBE input in
certain MCU bus interfaces.
Figure 29. Port C Structure
INTERNAL
DATA
BUS
DATA OUT
REG.
DQ
WR
MCELLBC[ 7:0]
ENABLE PRODUCT TERM (.OE)
READ MUX
P
D
B
CPLD - INPUT
DIR REG.
INPUT
MACROCELL
ENABLE OUT
SPECIAL FUNCTION
1
SPECIAL FUNCTION
1
CONFIGURATION
BIT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT C PIN
DATA OUT
AI02888B
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