參數(shù)資料
型號(hào)： PSD813F4
英文描述： Flash In System Programmable Mirocomputer Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM)
中文描述： Flash在系統(tǒng)可編程Mirocomputer外設(shè)（閃速，在系統(tǒng)可編程微控制器外圍器件，100萬位閃速存儲(chǔ)器，256K位的EEPROM，16K的位的SRAM）
文件頁數(shù)： 81/130頁
文件大小： 650K
代理商： PSD813F4
Prelimnary
PSD813F Famly
77
9.6.1 Standard JTAGSignals
The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three
different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are
inputs, waiting for a serial command from an external JTAG controller device (such as
FlashLink or Automated Test Equipment). When the enabling command is received from the
external JTAG controller, TDO becomes an output and the JTAG channel is fully functional
inside the PSD. The same command that enables the JTAG channel may optionally enable
the two additional JTAG pins, TSTAT and TERR.
The following symbolic logic equation specifies the conditions enabling the four basic
JTAG pins (TMS, TCK, TDI, and TDO) on their respective Port C pins. For purposes of
discussion, the logic label JTAG_ON will be used. When JTAG_ON is true, the four pins are
enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD I/O.
JTAG_ON =
PSDsoft_enabled +
/* An NVM configuration bit inside the PSD is set by the designer
in the PSDsoft Configuration utility. This dedicates the pins for
JTAG at all times (compliant with IEEE 1149.1) */
Microcontroller_enabled +
/* The microcontroller can set a bit at run-time by writing to the
PSD register, JTAG Enable. This register is located at address
CSIOP + offset C7h. Setting the JTAG_ENABLE bit in this
register will enable the pins for JTAG use. This bit is cleared
by a PSD reset or the microcontroller. See Table 35 for bit
definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside the PSD can be used to
enable the JTAG pins. This PT has the reserved name
JTAGSEL. Once defined as a node in PSDabel, the designer
can write an equation for JTAGSEL. This method is used when
the Port C JTAG pins are multiplexed with other I/O signals.
It is recommended to logically tie the node JTAGSEL to the
JEN\ signal on the Flashlink cable when multiplexing JTAG
signals. See Application Note 54 for details.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
*
*
*
*
JTAG_ENABLE
Table 35. JTAGEnable Register
JTAGEnable
*
Bits 1-7 are not used and should set to 0.
Bit definitions:
JTAG_ENABLE 1 = JTAG Port is Enabled.
0 = JTAG Port is Disabled.
The
PSD813F
Functional
Blocks
(cont.)
相關(guān)PDF資料
PDF描述
PSD813F Flash In-System-Programmable Microcontroller Peripherals(閃速，在系統(tǒng)可編程微控制器外圍器件，1M位閃速存儲(chǔ)器，256K位EEPROM，16K位SRAM)
PSD813FH(中文) Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器)
PSD813FN(中文) Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場可編程微控制器)
PSD813FN Field Programmble Microcontroller Peripherals(帶閃存的現(xiàn)場可編程微控制器)
PSD813FH Field Programmble Microcontroller Peripherals With Flash Memory(帶閃存的現(xiàn)場可編程微控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813F4-15J 制造商:WSI 功能描述:
PSD813F4-15JI 制造商:WSI 功能描述:
PSD813F4A-90J 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD813F2A-90J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD813F4A-90M 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD813F2A-90M RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
PSD813F4VA-15J 功能描述:SPLD - 簡單可編程邏輯器件 U 511-PSD813F2VA-15J RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
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