參數(shù)資料
型號(hào): PSD813F3V
英文描述: 60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a UB Surface Mount package; Similar to IRHLUB7970Z4 with optional Total Dose Rating of 300kRads
中文描述: Flash在系統(tǒng)編程(ISP)外設(shè)的8位微控制器
文件頁數(shù): 52/103頁
文件大?。?/td> 1185K
代理商: PSD813F3V
PSD81XFX, PSD83XF2, PSD85XF2
52/103
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 7. The addresses in Table 7 are the
offsets in hexadecimal from the base of the CSIOP
register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 22, are used for setting the
Port configurations. The default Power-up state for
each register in Table 22 is 00h.
Control Register.
Any bit reset to 0 in the Control
Register sets the corresponding port pin to MCU I/
O Mode, and a 1 sets it to Address Out Mode. The
default mode is MCU I/O. Only Ports A and B have
an associated Control Register.
Direction Register.
The Direction Register, in
conjunction with the output enable (except for Port
D), controls the direction of data flow in the I/O
Ports. Any bit set to 1 in the Direction Register
causes the corresponding pin to be an output, and
any bit set to 0 causes it to be an input. The default
mode for all port pins is input.
Figure 25, page 54 and Figure 26, page 55 show
the Port Architecture diagrams for Ports A/B and
C, respectively. The direction of data flow for Ports
A, B, and C are controlled not only by the direction
register, but also by the output enable product
term from the PLD AND Array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin’s direction.
An example of a configuration for a Port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 25. Since
Port D only contains three pins (shown in Figure
28), the Direction Register for Port D has only the
three least significant bits active.
Drive Select Register.
The Drive Select Register
configures the pin driver as Open Drain or CMOS
for some port pins, and controls the slew rate for
the other port pins. An external pull-up resistor
should be used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
1. The default pin drive is CMOS.
Note that the slew rate is a measurement of the
rise and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to 1. The default rate is slow slew.
Table 26 shows the Drive Register for Ports A, B,
C, and D. It summarizes which pins can be config-
ured as Open Drain outputs and which pins the
slew rate can be set for.
Table 22. Port Configuration Registers (PCR)
Note: 1. See Table 26 for Drive Register bit definition.
Table 23. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 24. Port Pin Direction Control, Output
Enable P.T. Defined
Table 25. Port Direction Assignment Example
Register Name
Port
MCU Access
Control
A,B
WRITE/READ
Direction
A,B,C,D
WRITE/READ
Drive Select
1
A,B,C,D
WRITE/READ
Direction Register Bit
Port Pin Mode
0
Input
1
Output
Direction
Register Bit
Output Enable
P.T.
Port Pin Mode
0
0
Input
0
1
Output
1
0
Output
1
1
Output
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
0
0
0
0
1
1
1
相關(guān)PDF資料
PDF描述
PSD813F4V -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA597260 with Standard Packaging
PSD813F5V -60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA9064 with optional Total Dose Rating of 300kRads
PSD86 THREE PHASE RECTIFIER BRIDGE
PSF101 WORLD MAGNETICS ULTRA SENSITIVEPRESSURESWITCHES
PSG61 4 KEY BI-BI CALL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD813F3V-12 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PSD813F3V-12J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F3V-12JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F3V-12JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD813F3V-12JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs