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參數(shù)資料
| 型號(hào)： | PSD4256G6V |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS |
| 中文描述： | Flash在系統(tǒng)編程（ISP）外設(shè)的16位微控制器 |
| 文件頁數(shù)： | 76/100頁 |
| 文件大小： | 759K |
| 代理商： | PSD4256G6V |
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PSD4256G6V
76/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
The state of the PSD Reset (RESET) signal does
not interrupt (or prevent) JTAG operations if the
JTAG pins are dedicated by an NVM configuration
bit (via PSDsoft). However, Reset (RESET) will
prevent or interrupt JTAG operations if the JTAG
Enable Register (as shown in Table 21, page 22)
is used to enable the JTAG pins.
The PSD supports JTAG In-System-Programma-
bility (ISP) commands, but not Boundary Scan.
ST’s PSDsoft software tool and FlashLINK JTAG
programming cable implement the JTAG In-Sys-
tem-Programmability (ISP) commands.
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by a JTAG command received over the
four standard JTAG pins (TMS, TCK, TDI, and
TDO). They are used to speed Program and Erase
cycles by indicating status on PSD pins instead of
having to scan the status out serially using the
standard JTAG channel. See Application Note
AN1153.
TERR indicates if an error has occurred when
erasing a sector or programming in Flash memory.
This signal goes Low (active) when an Error con-
dition occurs, and stays Low until a specific JTAG
command is executed or a Reset (RESET) pulse
is received after an “ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy (PE4)
described in the section entitled “Ready/Busy
(PE4)”, on page 26. TSTAT is High when the
PSD4256G6V device is in READ Mode (primary
Flash memory and secondary Flash memory con-
tents can be read). TSTAT is Low when Flash
memory Program or Erase cycles are in progress,
and also when data is being written to the second-
ary Flash memory.
TSTAT and TERR can be configured as open-
drain type signals with a JTAG command.
Note: The state of Reset (Reset) does not interrupt
(or prevent) JTAG operations if the JTAG signals
are dedicated by an NVM Configuration bit (via
PSDsoft). However, Reset (Reset) prevents or in-
terrupts JTAG operations if the JTAG Enable Reg-
ister (as shown in Table 21, page 22) is used to
enable the JTAG signals.
Security and Flash memory Protection
When the security bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a Full
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Full Chip Erase returns the device to
a non-secured blank state. The Security Bit can be
set in PSDsoft.
All primary Flash memory and secondary Flash
memory sectors can individually be sector protect-
ed against erasure. The sector protect bits can be
set in PSDsoft.
Table 52. JTAG Port Signals
INITIAL DELIVERY STATE
When delivered from ST, the PSD device has all
bits in the memory and PLDs set to 1. The PSD
Configuration Register bits are set to 0. The code,
configuration, and PLD logic are loaded using the
programming procedure. Information for program-
ming the device is available directly from ST.
Please contact your local sales representative.
Port E Pin
JTAG Signals
Description
PE0
TMS
Mode Select
PE1
TCK
Clock
PE2
TDI
Serial Data In
PE3
TDO
Serial Data Out
PE4
TSTAT
Status
PE5
TERR
Error Flag
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| PSD4256G6V-10UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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| PSD-45_11 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
| PSD-45A-05 | 功能描述:線性和開關(guān)式電源 30W 5Vout 6A Input 9.2-18VDC RoHS:否 制造商:TDK-Lambda 產(chǎn)品:Switching Supplies 開放式框架/封閉式:Enclosed 輸出功率額定值:800 W 輸入電壓:85 VAC to 265 VAC 輸出端數(shù)量:1 輸出電壓（通道 1）:20 V 輸出電流（通道 1）:40 A 商用/醫(yī)用: 輸出電壓（通道 2）: 輸出電流（通道 2）: 安裝風(fēng)格:Rack 長度: 寬度: 高度: |
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