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參數(shù)資料
| 型號： | PSD4256G6V |
| 廠商： | 意法半導體 |
| 英文描述： | FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 16-BIT MCUS |
| 中文描述： | Flash在系統(tǒng)編程（ISP）外設的16位微控制器 |
| 文件頁數(shù)： | 68/100頁 |
| 文件大?。?/td> | 759K |
| 代理商： | PSD4256G6V |
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PSD4256G6V
68/100
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Port E – Functionality and Structure
Port E can be configured to perform one or more
of the following functions (see Figure 31, page 69):
I
MCU I/O Mode
I
In-System Programming (ISP) – JTAG port can
be enabled for programming/erase of the PSD
device. (See the section entitled “RESET”, on
page 34, for more information on JTAG
programming.)
I
Open Drain – pins can be configured in Open
Drain Mode
I
Battery Backup features
– PE6 can be configured for a battery input sup-
ply, Voltage Standby (V
STBY
).
– PE7 can be configured as a Battery-on Indi-
cator (V
BATON
), indicating when V
CC
is less
than V
BAT
.
I
Latched Address output – Provide latched
address output.
Port F – Functionality and Structure
Port F can be configured to perform one or more
of the following functions:
I
MCU I/O Mode
I
CPLD Output – External Chip Select (ECS7-
ECS0) can be connected to Port F or Port C.
I
CPLD Input – direct input to the CPLD, no Input
Macrocells (IMC)
I
Latched Address output – Provide latched
address output as per Table 41, page 61.
I
Data Port – connected to D7-D0 when Port F is
configured as Data Port for a non-multiplexed
bus
I
Peripheral Mode
I
MCU RESET Mode – for 16-bit Motorola 683xx
and HC16 MCUs
Port G – Functionality and Structure
Port G can be configured to perform one or more
of the following functions:
I
MCU I/O Mode
I
Latched Address output – Provide latched
address output as per Table 41, page 61.
I
Open Drain – pins can be configured in Open
Drain Mode
I
Data Port – connected to D15-D8 when Port G
is configured as Data Port for a non-multiplexed
bus
I
MCU RESET Mode – for 16-bit Motorola 683xx
and HC16 MCUs
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4256G6V-10UI | 功能描述:CPLD - 復雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4-36 | 制造商:Tamura Corporation of America 功能描述: |
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