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參數(shù)資料
| 型號： | PSD4135G2 |
| 英文描述： | Flash In-System-Programmable Peripherals for 16-Bit MCUs(用于16位MCU的閃速在系統(tǒng)可編程外圍芯片) |
| 中文描述： | Flash在系統(tǒng)可編程外設(shè)的16位微控制器（用于16位微控制器的閃速在系統(tǒng)可編程外圍芯片） |
| 文件頁數(shù)： | 17/96頁 |
| 文件大?。?/td> | 515K |
| 代理商： | PSD4135G2 |
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Beta Information
PSD4000 Series
13
8.0
Register Bit
Definition
(cont.)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_Bit
*
*
*
Sec3_Prot
Sec2_Prot
Sec1_Prot Sec0_Prot
Flash Boot Protection Register
Bit definitions:
Sec<i>_Prot
Sec<i>_Prot
1 = Boot Block Sector <i> is write protected.
0 = Boot Block Sector <i> is not write protected.
Security_Bit
0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pgr7
Pgr6
Pgr5
Pgr4
Pgr3
Pgr2
Pgr1
Pgr0
Page Register
Bit definitions:
Configure Page input to PLD. Default Pgr[7:0] = 00.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
PLD
PLD
array-clk
PLD
Turbo
*
APD
enable
*
Mcells clk
PMMR0 Register
Bit definitions: (default is 0)
Bit 1 0 = Automatic Power Down (APD) is disabled.
1 = Automatic Power Down (APD) is enabled.
Bit 3 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
Bit 4 0 = CLKIN input to the PLD AND array is connected.
Every CLKIN change will power up the PLD when Turbo bit is off.
1 = CLKIN input to PLD AND array is disconnected, saving power.
Bit 5 0 = CLKIN input to the PLD Micro
Cells is connected.
1 = CLKIN input to the PLD Micro
Cells is disconnected, saving power.
*
Not used bit should be set to zero.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
PLD
PLD
PLD
PLD
PLD
*
*
array WRh
array Ale
array Cntl2 array Cntl1 array Cntl0
PMMR2 Register
Bit definitions (defauld is 0):
Bit 0 0 = Address A[7:0] are connected into the PLD array.
1 = Address A[7:0] are blocked from the PLD array, saving power.
Note: in XA mode, A3-0 come from PF3-0 and A7-4 come from ADIO7-4.
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
1 = Cntl0 input to the PLD AND array is disconnected, saving power.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
1 = Cntl1 input to the PLD AND array is disconnected, saving power.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
1 = Cntl2 input to the PLD AND array is disconnected, saving power.
Bit 5 0 = Ale input to the PLD AND array is connected.
1 = Ale input to the PLD AND array is disconnected, saving power.
Bit 6 0 = WRh/DBE input to the PLD AND array is connected.
1 = WRh/DBE input to the PLD AND array is disconnected, saving power.
*
Not used bit should be set to zero.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4135G2-12B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2-12B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
| PSD4135G2-12M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System-Programmable Peripherals for 16-Bit MCUs |
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