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參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 11/162頁(yè) |
| 文件大小： | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
108
Freescale Semiconductor
The RF data buffer consists of a small dedicated controller and a 128-bit data buffer. The RF data buffer is loaded with whatever
data pattern the user software creates. The number of data bits to be sent is selected by the FRM0:6 control bits. The control
logic is triggered by the SEND control bit when it is time to transmit the data and the complete data stream is sent to the RF stage
on the DATA line while being encoded as either Manchester or Bi-Phase data according to the method selected by the CODE bit.
Before the data can be transmitted the SEND control bit sets the RTS signal to enable the RF output stage to start up from its
low power standby condition. The control logic will not begin the transmission phase until it receives a high input on the CTS
signal from the RF stage which occurs after the RF PLL has stabilized. The type of RF transmission mode is controlled by the
MOD bit as described in Section 13.5.1.
The external crystal connected to the X0 and XI pins provides the carrier frequency as well as the data rate clock, DCLK, for the
data rates associated with the ASK or FSK modulation. Therefore the tolerance on the data rate will depend on the characteristics
of the external crystal. One of four data rates from the bit rate generator can be selected by the BPS0:1 as described in Table 13-4.
Once the data buffer is emptied the data transfer stops; the RF output stage is turned off; and the SEND control bit is cleared.
The user can test that the transmission has completed by reading back the state of the SEND control bit. If multiple frames of
data are to be transmitted within a datagram the spacing between frames must be controlled by the MCU. A block diagram of the
RF data buffer is shown in Figure 13-2.
NOTE
When using the data buffer mode the user’s software should not change any bits in the RFX other than the SEND
bit. Changing other RFX register contents can lead to data faults or errors.
Figure 13-2 RF Data Buffer Block Diagram
13.2.2
MCU Direct Mode
In the MCU direct mode the data to the RF output stage is driven directly from the MCU. In this mode the user software must
control the RF output stage to power up (using the SEND control bit), wait for the RF output stage to stabilize (monitor the RCTS
status bit) and clock the DATA to the RF output stage. In this mode the data rate and its stability will depend on the internal 8 MHz
oscillator.
Any transfers of data from the MCU will use the DX signal as modulated data on the RF pin once the RF output stage is set up
to transmit. The maximum data rate in this mode will depend on the complexity of the user software. The DX signal can be
controlled by the MCU PTCD1 pin internal to the MPXY8300 series package. PTCD1 can control the DX signal to the RF output
only when both the RFX CKREF and RFM bits are logical zero.
DATA
ENCODER
RF DATA BUFFER
MAX 128 BITS
CONTROL
LOGIC
DATA
RTS
OUTPUT
DRIVER
BIT
RATE GEN
DCLK
DATA
CTS
TO
/F
ROM
RF
O
U
TPUT
STAG
E
ADDR
RW
DATA
MUX
RFM
SEND
CODE
BPS0:7
FRM0:6
POL
RCTS
EOM
RFEF
DX
CKREF
(PTCD1)
RFM
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