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| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 103/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
45
6.3
Parallel I/O Registers
This section provides information about the registers associated with the Port A parallel I/O and pin control functions. These
parallel I/O registers are located in page zero of the memory map and the pin control registers are located in the high page register
section of memory.
Refer to tables in Section 4, for the absolute address assignments for all parallel I/O and pin control registers. This section refers
to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to
translate these names into the appropriate absolute addresses.
Port A parallel I/O function is controlled by the registers described in this section.
Table 6-1 Truth Table for Pull-up and Pull-down Resistors(1)
NOTES:
1. x = Don’t care
Line No.
PTAPEm
PTADDm
KBIPEn
KBEDGn
Pull-up
Pull-down
1
0
x
Disabled
2
1
0
x
Enabled
Disabled
3
x
1
0
x
Disabled
4
0
1
x
Disabled
5
1
0
1
0
Enabled
Disabled
6
1
0
1
Disabled
Enabled
7
x
1
x
Disabled
7
6
5
4
3
2
1
0
R
0
W
Reset:
0
Figure 6-1 Port A Data Register (PTAD)
Table 6-2 Port A Data Register Field Descriptions
Field
Description
6:0
PTADn
Port A Data Register Bit n (n = 0–6) — For port A pins that are inputs, reads return the logic level on the pin.
For port A pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also config-
ures all port pins as high-impedance inputs with pull-ups disabled.
7
6
5
4
3
2
1
0
R
0
W
Reset:
0
Figure 6-2 Internal Pull-up Enable for Port A Register (PTAPE)
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