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參數(shù)資料
| 型號(hào)： | POE-VOICE-RD |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 42/108頁(yè) |
| 文件大小： | 0K |
| 描述： | KIT REF DESIGN PWR OVER ETHERNET |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 參考設(shè)計(jì)，以太網(wǎng)供電（POE），語(yǔ)音傳輸 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | C8051F340，CP2201，Si3400 |
| 主要屬性： | 嵌入式以太網(wǎng)，以太網(wǎng)供電，8 kHz 語(yǔ)音采樣系統(tǒng) |
| 次要屬性： | 圖形用戶界面 |
| 已供物品： | 板，線纜，電源，軟件 |
| 產(chǎn)品目錄頁(yè)面： | 626 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 336-1385-ND - IC POWER OVER ETHERNET 20QFN 336-1322-ND - IC POWER OVER ETHERNET 20QFN 336-1313-ND - IC ETH CTRLR SNGL-CHIP 28QFN 336-1298-ND - IC 8051 MCU FLASH 64K 48TQFP |
| 其它名稱： | 336-1326 |
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CP2200/1
Rev. 1.0
39
9.2. Power-fail
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor will
drive the /RST pin low and return the CP2200/1 to the reset state. When VDD returns to a level above VRST, the
CP2200/1 will be released from the reset state as shown in Figure 14.
The power supply monitor circuit (VDD Monitor) is enabled and selected as a reset source by hardware following
every power-on reset. To prevent the device from being held in reset when VDD drops below VRST, the VDD Monitor
may be deselected as a reset source (see RSTEN on page 42) and disabled (see VDMCN on page 39). It is
recommended to leave the VDD Monitor enabled and selected as a reset source at all times.
Register 11. VDMCN: VDD Monitor Control Register
9.3. Oscillator-Fail Reset
If the system clock derived from the oscillator fails for any reason after oscillator initialization is complete, the reset
circuitry will drive the /RST pin low and return the CP2200/1 to the reset state. The CP2200/1 will remain in the
reset state for approximately 1 ms then exit the reset state in the same manner as that for the power-on reset.
9.4. External Pin Reset
The external /RST pin provides a means for external circuitry to force the CP2200/1 into a reset state. Asserting the
/RST pin low will cause the CP2200/1 to enter the reset state. It is recommended to provide an external pull-up
and/or decoupling capacitor of the /RST pin to avoid erroneous noise-induced resets. The CP2200/1 will exit the
reset state approximately 4 s after a logic high is detected on /RST.
Bit 7:
VDMEN: VDD Monitor Enable
This bit can be used to disable or enable the VDD Monitor Circuit. Note: The VDD Monitor circuit is
enabled and selected as a reset source following every power-on reset. If the VDD Monitor is
disabled and then reenabled during device operation, it must be allowed to stabilize before it is
selected as a reset source. Selecting the VDD Monitor as a reset source before it has stabilized will
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
Bit6:
VDDSTAT: VDD Status
This bit indicates the current power supply status (VDD Monitor output).
0: VDD voltage is at or below the VDD Monitor threshold.
1: VDD voltage is above the VDD Monitor threshold.
Bits 5–0: RESERVED. Read = varies; Write = don’t care.
R/W
R
RRR
RR
Reset Value
VDMEN
VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x13
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