參數(shù)資料
型號： PNX8526EH
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： Programmable source decoder with integrated peripherals
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA456
封裝： 35 X 35 MM, 1.8 MM HEIGHT, PLASTIC, MS-034, SOT610-1, HBGA-456
文件頁數(shù)： 49/59頁
文件大?。?/td> 3319K
代理商： PNX8526EH
Philips Semiconductors
PNX8526
Programmable Source Decoder with Integrated Peripherals
Preliminary data
Rev. 01 – 6 October 2003
49 of 59
9397 750 11715
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
13.10 Sony Philips Digital Interface (SPDIF) timing
13.11 Digital Video Output (DV Out) timing
Table 32:
Symbol
AO_SCK
t
SCK(DV)
t
su(SCK)
t
h_SCK
t
ws(SCK)
I2S audio output
Parameter
Audio Out to AO_SCK clock frequency
AO_SCK to AO_SC valid
Input Setup Time to AO_SCK (Audio interface as slave)
Input Hold Time from AO_SCK (Audio interface as slave)
AO_SCK to AO_WS
Min Max Unit
-
20
2
-
2
-
2
-
-
10
MHz
ns
ns
ns
ns
Fig 15. SPDIF timing
Table 33:
Symbol
t
HIGH
t
LOW
SPDIF timing
Parameter
CLK High Time (PCI)
CLK Low Time (PCI)
Min
-
-
Typical
5.2
5.2
Max
-
-
Unit
μ
s
μ
s
handbook, 4 columns
MCE553
tHIGH
tLOW
Fig 16. DV Out timing
Table 34:
Symbol
DV_CLK
t
CLK(DV)
t
su(CLK)
t
h(CLK)
DV Out timing
Parameter
Video out clock frequency
DV_CLK to DV_OUT
VSYNC Setup Time to DV_CLK (as input)
CRT Control Hold Time from DV_CLK
HSYNC, VSYNC, BLANK
Min
27
-3.7
3
0
Max
-
0
-
-
Unit
MHz
[1]
ns
ns
ns
handbook, 4 columns
valid
DV_CLK
HSYNC
VSYNC
BLANK
DV_OUT
(Data)
valid
MCE554
tsu(CLK)
th(CLK)
tCLK(DV)
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