Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
12NC 9397 750 14321
Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Product data sheet
Rev. 2 — 1 December 2004
23-24
1
RxErrorIntEn
R/W
Enable interrupts on receive errors.
0
RxOverrunIntEn
R/W
Enable interrupts on receive buffer overrun or descriptor underrun
conditions.
Interrupt Clear Register (IntClear)
Offset 0x07 2FE8
The Interrupt Clear register is write-only. Writing a 1 to a bit of the register clears the corresponding bit in the Status register.
Writing a 0 to a bit of the register does not affect the corresponding interrupt status.
31:14
-
-
Unused
13
WakeupIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
12
SoftIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
11
TxRtDoneIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
10
TxRtFinishedIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
9
TxRtErrorIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
8
TxRtUnderrunIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
7
TxDoneIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
6
TxFinishedIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
5
TxErrorIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
4
TxUnderrunIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
3
RxDoneIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
2
RxFinishedIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
1
RxErrorIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
0
Offset 0x07 2FEC
RxOverrunIntSet
WO
Writing a 1 clears the corresponding status bit in IntStatus.
Interrupt Set Register (IntSet)
The interrupt set register is write-only. Writing a 1 to a bit of the register sets the corresponding bit in the Status register.
Writing a 0 to a bit of the register does not affect the interrupt status.
31:14
-
-
Unused
13
WakeupIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
12
SoftIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
11
TxRtDoneIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
10
TxRtFinishedIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
9
TxRtErrorIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
8
TxRtUnderrunIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
7
TxDoneIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
6
TxFinishedIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
5
TxErrorIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
4
TxUnderrunIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
3
RxDoneIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
2
RxFinishedIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
1
RxErrorIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
0
RxOverrunIntSet
WO
Writing a 1 sets the corresponding status bit in IntStatus.
Table 2: LAN100 Registers
…Continued
Bit
Symbol
Acces
s
Value
Description