Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 23: LAN100 — Ethernet Media Access Controller
12NC 9397 750 14321
Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Product data sheet
Rev. 2 — 1 December 2004
23-15
The values represent the status of the three channels/datapaths. In case the status is 1 the channel is active meaning it:
is enabled and the Rx/TxRt/TxEnable bit is set in the Command register or it just got disabled while still transmitting or
receiving a frame
and for transmit channels the transmit queue is not empty i.e. ProduceIndex != ConsumeIndex
and for the receive channel the receive queue is not full i.e. ProduceIndex != ConsumeIndex - 1
The status transitions from active to inactive if the channel is disabled by software resetting the Tx/Rt/TxRtEnable bit in the
Command register and if the channel has committed the status and data of the current frame to memory. The status also
transition to inactive if the transmit queue is empty or if the receive queue is full and status and data have been committed to
memory.
31:3
-
-
Unused
2
TxRtStatus
RO
If ‘1’, the real-time transmit datapath is active. If ‘0’, the channel is
inactive.
1
TxStatus
RO
If ‘1’, non-real-time transmit datapath is active. If ‘0’, the channel is
inactive.
0
Offset 0x07 2108
RxStatus
RO
If ‘1’, the receive datapath is active, if ‘0’, the channel is inactive.
Receive Descriptor Base Address Register (RxDescriptor)
The receive descriptor base address is a byte address aligned to a word boundary, (i.e. the two LSBs of the address are
fixed to 0). The register contains the lowest address in the array of descriptors.
31:2
RxDescriptor
R/W
0
MSBs of receive descriptor base address.
1:0
Offset 0x07 210c
-
RO
0
Fixed to 0.
Receive Status Base Address Register (RxStatus)
The receive status base address is a byte address aligned to a double word boundary i.e. LSB 2:0 are fixed to 3’b000.
31:3
RxStatus
R/W
0
MSBs of receive status base address.
2:0
Offset 0x07 2110
-
RO
0
Fixed to 0.
Receive Number of Descriptors Register (RxDescriptorNumber)
This register defines the number of descriptors in the descriptor array for which RxDescriptor is the base address. The
number of descriptors should match the number of states. The register uses minus-one encoding, i.e. if the array has 8
status elements, the value in the register should be 7.
31:16
-
-
Unused
15:0
RxDescriptorNumber
R/W
0
Number of descriptors in the descriptor array for which RxDescriptor
is the base address. The number of descriptors is minus-one
encoded.
Receive Produce Index (RxProduceIndex)
Offset 0x07 2114
This register indexes the descriptor that is going to be filled next by the Receive Datapath. After a packet has been received,
hardware increments the index and wrapps to 0 when the value of RxDescriptorNumber has been reached. If the
RxProduceIndex equals RxConsumeIndex – 1, the array is full, and any further packets being received will cause a buffer
overrun error.
31:16
-
-
Unused
15:0
Rx Produce Index
RO
Index of the descriptor that is going to be filled next by the Receive
Datapath.
Receive Consume Index (RxConsumeIndex)
Offset 0x07 2118
Table 2: LAN100 Registers
…Continued
Bit
Symbol
Acces
s
Value
Description