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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC18F4539-I/ML
寤犲晢锛� Microchip Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 61/322闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU FLASH 12KX16 EE A/D 44QFN
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Asynchronous Stimulus
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 45
绯诲垪锛� PIC® 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 40MHz
閫ｉ€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孡VD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 24KB锛�12K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 256 x 8
RAM 瀹归噺锛� 1408 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.2 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 44-VQFN 瑁搁湶鐒婄洡(p谩n)
鍖呰锛� 绠′欢
閰嶇敤锛� 444-1001-ND - DEMO BOARD FOR PICMICRO MCU
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2002 Microchip Technology Inc.
Preliminary
DS30485A-page 151
PIC18FXX39
16.4.7
BAUD RATE GENERATOR
In I2C Master mode, the baud rate generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 16-17). When a write occurs
to SSPBUF, the baud rate generator will automatically
begin counting. The BRG counts down to 鈥�0鈥� and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 15-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 16-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 16-3:
I2C CLOCK RATE W/BRG
SSPM3:SSPM0
BRG Down Counter
CLKO
FOSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
FCY
FCY*2
BRG Value
FSCL(2)
(2 Rollovers of BRG)
10 MHz
20 MHz
19h
400 kHz(1)
10 MHz
20 MHz
20h
312.5 kHz
10 MHz
20 MHz
3Fh
100 kHz
4 MHz
8 MHz
0Ah
400 kHz(1)
4 MHz
8 MHz
0Dh
308 kHz
4 MHz
8 MHz
28h
100 kHz
1 MHz
2 MHz
03h
333 kHz(1)
1 MHz
2 MHz
0Ah
100kHz
1 MHz
2 MHz
00h
1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2: Actual frequency will depend on bus conditions. Theoretically, bus conditions will add rise time and extend
low time of clock period, producing the effective frequency.
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
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PIC18F4539T-E/ML 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 24KB 1408 RAM 32 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F4539T-E/PT 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 24KB 1408 RAM 32 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
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