2009 Microchip Technology Inc.
DS39761C-page 305
PIC18F2682/2685/4682/4685
23.2.3.2
Message Acceptance Filters
and Masks
This section describes the message acceptance filters
and masks for the CAN receive buffers.
REGISTER 23-37: RXFnSIDH: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER
REGISTERS, HIGH BYTE [0
≤ n ≤ 15](1)
R/W-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
SID10:SID3: Standard Identifier Filter bits (if EXIDEN = 0)
Extended Identifier Filter bits EID28:EID21 (if EXIDEN = 1).
Note 1:
Registers RXF6SIDH:RXF15SIDH are available in Mode 1 and 2 only.
REGISTER 23-38: RXFnSIDL: RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER
REGISTERS, LOW BYTE [0
≤ n ≤ 15](1)
R/W-x
U-0
R/W-x
U-0
R/W-x
SID2
SID1
SID0
—
EXIDEN(2)
—EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
SID2:SID0: Standard Identifier Filter bits (if EXIDEN = 0)
Extended Identifier Filter bits EID20:EID18 (if EXIDEN = 1).
bit 4
Unimplemented: Read as ‘0’
bit 3
EXIDEN: Extended Identifier Filter Enable bit(2)
1 = Filter will only accept extended ID messages
0 = Filter will only accept standard ID messages
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID17:EID16: Extended Identifier Filter bits
Note 1:
Registers RXF6SIDL:RXF15SIDL are available in Mode 1 and 2 only.
2:
In Mode 0, this bit must be set/cleared as required, irrespective of corresponding mask register value.
