參數(shù)資料
型號(hào)： PIC16C711-04/P
廠商： Microchip Technology
文件頁數(shù)： 98/177頁
文件大?。?/td> 0K
描述： IC MCU OTP 1KX14 A/D 18DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 25
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 13
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類型： OTP
RAM 容量： 68 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 18-DIP（0.300"，7.62mm）
包裝： 管件
配用： ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1059-ND - ADAPTER 18 ZIF BD W/18SO PLUGS
DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
1997 Microchip Technology Inc.
DS30272A-page 27
PIC16C71X
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
EXAMPLE 5-2:
INITIALIZING PORTB
BCF
STATUS, RP0
;
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
BSF
STATUS, RP0
; Select Bank 1
MOVLW
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISB
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION<7>). The
weak pull-up is automatically turned off when the port
pin is congured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 5-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
Data Latch
RBPU(2)
P
VDD
Q
D
CK
Q
D
CK
Q
D
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
RB0/INT
I/O
pin(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: TRISB = ’1’ enables weak pull-up if
RBPU = ’0’ (OPTION<7>).
Schmitt Trigger
Buffer
TRIS Latch
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins congured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
gured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with ag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
a)
Any read or write of PORTB. This will end the
mismatch condition.
b)
Clear ag bit RBIF.
A mismatch condition will continue to set ag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow ag bit RBIF to be cleared.
This interrupt on mismatch feature, together with soft-
ware congurable pull-ups on these four pins allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook,
"Implementing Wake-Up on Key
Stroke" (AN552).
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
Note:
For the PIC16C71
if a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then interrupt ag bit
RBIF may not get set.
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