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參數(shù)資料
| 型號： | PIC14000T-20/SS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 135/153頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 4KX14 A/D 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,100 |
| 系列： | PIC® 14 |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C |
| 外圍設(shè)備： | POR，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 20 |
| 程序存儲器容量： | 7KB（4K x 14） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 192 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | 斜率 A/D |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
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PIC14000
DS40122B-page 82
Preliminary
1996 Microchip Technology Inc.
10.6
Interrupts
The PIC14000 has several sources of interrupt:
External interrupt from OSC1/PBTN pin
I2C port interrupt
PORTC interrupt on change (pins RC<7:4> only)
Timer0 overow
A/D timer overow
A/D converter capture event
Programmable reference comparator interrupt
This section addresses the external and Timer0
interrupts only. Refer to the appropriate sections for
description of the serial port, programmable reference
and A/D interrupts.
INTCON records individual interrupt requests in ag
bits. It also has individual and global enable bits. The
peripheral interrupt ags reside in the PIR1 register.
Peripheral interrupt enable interrupts are contained in
the PIE1 register.
Global
interrupt
masking
is
controlled
by
GIE
(INTCON<7>). Individual interrupts can be disabled
through their corresponding mask bit in the INTCON
register. GIE is cleared on reset to mask interrupts.
When an interrupt is serviced, the GIE is cleared to
disable any further interrupt, the return address is
pushed onto the stack and the PC is loaded with
0004h, the interrupt vector. For external interrupt
events, such as the I2C interrupt, the interrupt latency
will be 3 or 4 instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for 1 or 2 cycle instructions. Once in the
interrupt service routine the source(s) of the interrupt
can be determined by polling the interrupt ag bits. The
interrupt ag bit(s) must be cleared in software before
re-enabling
interrupts
to
avoid
innite
interrupt
requests.
Individual
interrupt
ag
bits
are
set
regardless of the status of their corresponding mask bit
or the GIE bit to allow polling.
The return from interrupt instruction, RETFIE, exits the
interrupt routine as well as sets the GIE bit to re-enable
interrupts.
Note 1: The individual interrupt ags will be set by
the specied condition even though the
corresponding
interrupt
enable
bit
is
cleared (interrupt disabled) or the GIE bit is
cleared (all interrupts disabled).
Note 2: If an interrupt occurs while the Global
Interrupt Enable (GIE) bit is being cleared,
the
GIE
bit
may
unintentionally
be
re-enabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
1.
An instruction clears the GIE bit while an
interrupt is acknowledged.
2.
The program branches to the interrupt vector
and executes the Interrupt Service Routine.
3.
The interrupt service routine completes with the
execution of the RETFIE instruction. This causes
the GIE bit to be set (enables interrupts), and the
program returns to the instruction after the one
which was meant to disable interrupts.
The method to ensure that interrupts are globally
disabled is:
1.
Ensure that the GIE bit was cleared by the
instruction, as shown in the following code:
LOOP: BCF
INTCON,GIE
; Disable Global Interrupts
BTFSC INTCON,GIE
; Global Interrupts Disabled?
GOTO
LOOP
; No, try again
:
; Yes, continue with program
;
flow
FIGURE 10-9: INTERRUPT LOGIC SCHEMATIC
PBIF
PBIE
ADCIF
ADCIE
I2CIF
I2CIE
OVFIF
OVFIE
CMIF
CMIE
T0IF
T0IE
PEIE
Wake-up (If in SLEEP mode)
or terminate long write
Interrupt to CPU
PEIF
RCIF
RCIE
GIE
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