參數(shù)資料
型號(hào): PIC14000T-20/SS
廠商: Microchip Technology
文件頁數(shù): 133/153頁
文件大?。?/td> 0K
描述: IC MCU OTP 4KX14 A/D 28SSOP
標(biāo)準(zhǔn)包裝: 2,100
系列: PIC® 14
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C
外圍設(shè)備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 7KB(4K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: 斜率 A/D
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
PIC14000
DS40122B-page 80
Preliminary
1996 Microchip Technology Inc.
10.5.5
TIMEOUT SEQUENCE
On power-up the time-out sequence is as follows: First
the PWRT time-out is invoked after POR has expired.
The OST is activated only in HS (crystal oscillator)
mode. The total time-out will vary based on the oscilla-
tor conguration and PWRTE status. For example, in
IN mode, with PWRTE unprogrammed (PWRT dis-
abled), there will be no time-out delay at all.
Figure 13-4 depicts the power-on reset time-out
sequences.
Table 10-4 shows the reset conditions for some special
registers, while Table 10-5 shows the reset conditions
for all registers.
FIGURE 10-8: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
1.
External power-on reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2.
R < 40 K
is recommended to make sure
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5
A). A larger voltage drop will
degrade VIH level on MCLR pin.
3.
R1 = 100
to 1 K will limit any current
owing into MCLR from external capacitor C
in the event of MCLR pin breakdown due to
ESD or EOS.
PIC14000
MCLR
VDD
D
C
R1
R
VDD
TABLE 10-4:
RESET CONDITION FOR SPECIAL REGISTERS
Legend: u = unchanged
x = unknown
- = unimplemented, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
Condition
PCL
Addr: 02h
STATUS
Addr: 03h
PCON
Addr: 8Eh
Power-on Reset
000h
0001 1xxx
0--- --0x
MCLR reset during normal operation
000h
0001 1uuu
u--- --ux
MCLR reset during SLEEP
000h
0001 0uuu
u--- --ux
WDT reset during normal operation
000h
0000 1uuu
u--- --ux
WDT during SLEEP
PC + 1
uuu0 0uuu
u--- --ux
Interrupt wake-up from SLEEP
PC + 1(1)
uuu1 0uuu
u--- --ux
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