參數(shù)資料
型號(hào)： PIC14000T-20/SS
廠商： Microchip Technology
文件頁數(shù)： 13/153頁
文件大?。?/td> 0K
描述： IC MCU OTP 4KX14 A/D 28SSOP
標(biāo)準(zhǔn)包裝： 2,100
系列： PIC® 14
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 20
程序存儲(chǔ)器容量： 7KB（4K x 14）
程序存儲(chǔ)器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： 斜率 A/D
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 11
PIC14000
3.1
Clocking Scheme/Instruction Cycle
The clock input (from OSC1 or the internal oscillator) is
internally
divided
by
four
to
generate
four
non-overlapping quadrature clocks, namely Q1, Q2,
Q3 and Q4. The program counter (PC) is incremented
every Q1, the instruction is fetched from the program
memory and latched into the instruction register in Q4.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution ow are shown in Figure 3-2.
3.2
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
CLKOUT
(IN mode)
PC
PC+1
PC+2
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
Internal
Phase
Clock
1. MOVLW
55h
2. MOVWF
PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3
Fetch 1
Fetch 2
Fetch 3
Fetch SUB_1
Execute 1
Flush
All instructions are single cycle, except for program branches. These take two cycles
since the fetched instruction is “flushed” from the pipeline while the new instruction is
being fetched and then executed.
Execute 2
Flush
Fetch 4
Fetch SUB_1
Execute 3
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