參數(shù)資料
型號： PIC12F683-I/MD
廠商： Microchip Technology
文件頁數(shù)： 37/176頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 2KX14 8DFN
產(chǎn)品培訓模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
Digi-Key 應用說明： AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
標準包裝： 91
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 5
程序存儲器容量： 3.5KB（2K x 14）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-VDFN 裸露焊盤
包裝： 管件
產(chǎn)品目錄頁面： 645 (CN2011-ZH PDF)
配用： AC164326-ND - MODULA SKT PM3 20QFN
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
2007 Microchip Technology Inc.
DS41211D-page 129
PIC12F683
TABLE 15-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C
≤ TA ≤ +125°C
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCLMCLR Pulse Width (low)
2
5
—
μs
VDD = 5V, -40°C to +85°C
VDD = 5V
31
TWDT
Watchdog Timer Time-out
Period (No Prescaler)
10
16
29
31
ms
VDD = 5V, -40°C to +85°C
VDD = 5V
32
TOST
Oscillation Start-up Timer
Period(1, 2)
—
1024
—
TOSC (NOTE 3)
33*
TPWRT
Power-up Timer Period
40
65
140
ms
34*
TIOZ
I/O High-impedance from
MCLR Low or Watchdog Timer
Reset
——
2.0
μs
35
VBOR
Brown-out Reset Voltage
2.0
—
2.2
V
(NOTE 4)
36*
VHYST
Brown-out Reset Hysteresis
—
50
—
mV
37*
TBOR
Brown-out Reset Minimum
Detection Period
100
—
μsVDD ≤ VBOR
*
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-
ation and/or higher than expected current consumption. All devices are tested to operate at “min” values
with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time
limit is “DC” (no clock) for all devices.
2:
By design.
3:
Period of the slower clock.
4:
To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1
μF and 0.01 μF values in parallel are recommended.
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