參數(shù)資料
型號： PIC12F683-I/MD
廠商： Microchip Technology
文件頁數(shù)： 167/176頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 2KX14 8DFN
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
Digi-Key 應(yīng)用說明： AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
標(biāo)準(zhǔn)包裝： 91
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 5
程序存儲器容量： 3.5KB（2K x 14）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-VDFN 裸露焊盤
包裝： 管件
產(chǎn)品目錄頁面： 645 (CN2011-ZH PDF)
配用： AC164326-ND - MODULA SKT PM3 20QFN
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
PIC12F683
DS41211D-page 88
2007 Microchip Technology Inc.
12.3.6
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
PWRT time-out is invoked after POR has expired.
OST is activated after the PWRT time-out has
expired.
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in EC
mode with PWRTE bit erased (PWRT disabled), there
will be no time-out at all. Figure 12-4, Figure 12-5 and
Figure 12-6 depict time-out sequences. The device can
execute code from the INTOSC while OST is active by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to synchronize more than one PIC12F683 device
operating in parallel.
Table 12-5 shows the Reset conditions for some
special registers, while Table 12-4 shows the Reset
conditions for all the registers.
12.3.7
POWER CONTROL (PCON)
REGISTER
The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset occurred
last.
Bit 0 is BOR (Brown-out). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable
if
the
brown-out
circuit
is
disabled
(BOREN<1:0>
= 00 in the Configuration Word
register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a subse-
quent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
For more information, see Section 4.2.4 “Ultra
and
TABLE 12-1:
TIME-OUT IN VARIOUS SITUATIONS
TABLE 12-2:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
TABLE 12-3:
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Oscillator Configuration
Power-up
Brown-out Reset
Wake-up from
Sleep
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
XT, HS, LP
TPWRT + 1024
TOSC
1024 TOSC
TPWRT + 1024
TOSC
1024 TOSC
RC, EC, INTOSC
TPWRT
—TPWRT
——
POR
BOR
TO
PD
Condition
0x11
Power-on Reset
u011
Brown-out Reset
uu0u
WDT Reset
uu00
WDT Wake-up
uuuu
MCLR Reset during normal operation
uu10
MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
Name
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets(1)
CONFIG(2)
BOREN1
BOREN0
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
—
PCON
—
ULPWUE SBOREN
—
—POR
BOR
--01 --qq
--0u --uu
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
Legend:
u
= unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR.
Note
1:
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2:
See Configuration Word register (Register 12-1) for operation of all register bits.
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