2007 Microchip Technology Inc.
DS41211D-page 37
PIC12F683
4.2.5.2
GP1/AN1/CIN-/VREF/ICSPCLK
Figure 4-2 shows the diagram for this pin. The GP1 pin
is configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a analog input to the comparator
a voltage reference input for the ADC
In-Circuit Serial Programming clock
FIGURE 4-2:
BLOCK DIAGRAM OF GP1
4.2.5.3
GP2/AN2/T0CKI/INT/COUT/CCP1
Figure 4-3 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
the clock input for Timer0
an external edge triggered interrupt
a digital output from the Comparator
a digital input/output for the CCP (refer to
FIGURE 4-3:
BLOCK DIAGRAM OF GP2
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Data
WR
WPU
RD
WPU
RD GPIO
RD
GPIO
WR
GPIO
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
Interrupt-on-
To Comparator
Analog
Input Mode(1)
GPPU
Analog
Input Mode(1)
change
Bus
Note 1: Comparator mode and ANSEL determines Analog
Input mode.
Q3
To A/D Converter
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data
WR
WPU
RD
WPU
RD
GPIO
WR
GPIO
WR
TRISIO
RD
TRISIO
WR
IOC
RD
IOC
To A/D Converter
0
1
COUT
Enable
To INT
To Timer0
Analog
Input Mode
GPPU
RD GPIO
Analog
Input
Mode
Interrupt-on-
change
Bus
Q3
Note
1:
Comparator mode and ANSEL determines Analog
Input mode.