參數(shù)資料
型號(hào)： PIC12F635-I/SN
廠商： Microchip Technology
文件頁(yè)數(shù)： 43/74頁(yè)
文件大?。?/td> 0K
描述： IC MCU FLASH 1KX14 8SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 100
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 637 (CN2011-ZH PDF)
配用： AC162057-ND - MPLAB ICD 2 HEADER 14DIP
Micrel, Inc.
KSZ8841-PMQL
October 2007
48
M9999-100407-1.5
Wakeup Frame 0 CRC0 Register (Offset 0x0220): WF0CRC0
This register contains the expected CRC values of the Wake up frame 0 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, taken over the bytes specified in the
wake up byte mask registers.
Bit
Default
R/W
Description
15 - 0
--
RW
WF0CRC0
Wake up Frame 0 CRC (lower 16 bits)
The expected CRC value of a wake up frame 0 pattern.
Wakeup Frame 0 CRC1 Register (Offset 0x0222): WF0CRC1
This register contains the expected CRC values of the Wake up frame 0 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, taken over the bytes specified in the
wake up byte mask registers.
Bit
Default
R/W
Description
15 - 0
--
RW
WF0CRC1
Wake up Frame 0 CRC (upper 16 bits)
The expected CRC value of a wake up frame 0 pattern.
Wakeup Frame 0 Byte Mask 0 Register (Offset 0x0224): WF0BM0
This register contains the first 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the first byte
of the Wake up frame 0; setting bit 15 selects the 16th byte of the Wake up frame 0.
Bit
Default
R/W
Description
15 - 0
--
RW
WF0BM0
Wake up Frame 0 Byte Mask 0
The first 16 bytes mask of a wake up frame 0 pattern.
Wakeup Frame 0 Byte Mask 1 Register (Offset 0x0226): WF0BM1
This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 0; setting bit 15 selects the 32nd byte of the Wake up frame 0.
Bit
Default
R/W
Description
15 - 0
--
RW
WF0BM1
Wake up Frame 0 Byte Mask 1
The next 16 bytes mask covering bytes 17 to 32 of a wake up frame 0
pattern.
Wakeup Frame 0 Byte Mask 2 Register (Offset 0x0228): WF0BM2
This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 0; setting bit 15 selects the 48th byte of the Wake up frame 0.
Bit
Default
R/W
Description
15 - 0
--
RW
WF0BM2
Wake up Frame 0 Byte Mask 2
The next 16 bytes mask covering bytes 33 to 48 of a wake up frame 0
pattern.
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