參數(shù)資料
型號(hào): PIC12F635-I/SN
廠商: Microchip Technology
文件頁(yè)數(shù): 22/74頁(yè)
文件大?。?/td> 0K
描述: IC MCU FLASH 1KX14 8SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 100
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 5
程序存儲(chǔ)器容量: 1.75KB(1K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 637 (CN2011-ZH PDF)
配用: AC162057-ND - MPLAB ICD 2 HEADER 14DIP
Micrel, Inc.
KSZ8841-PMQL
October 2007
29
M9999-100407-1.5
Configuration ID Register (CFID Offset 00H)
The CFID register identifies the KSZ8841-PMQL. The following table shows the CFID register bit fields.
Bit
Default
Description
31 - 16
0x8841
Device ID
15 - 0
0x16C6
Vendor ID
Specifies the manufacturer of the KSZ8841-PMQL.
The following table shows the access rules of the register.
Command and Status Configuration Register (CFCS Offset 04H)
The CFCS register is divided into two sections: a command register (CFCS[15:0]) and a status register (CFCS[31:16]).
The command register provides control of the KSZ8841-PMQL’s ability to generate and respond to PCI cycles. When 0
is written to this register, the KSZ8841-PMQL logically disconnects from the PCI bus for all accesses except
configuration accesses.
The status register records status information for the PCI bus-related events. The CFCS status bits are not cleared
when they are read. Writing 1 to these bits clears them; writing 0 has no effect.
The following table describes the CFCS register bit fields.
Bit
Type
Default
Description
31
Status
0
Detected Parity Error
When set, indicates that the KSZ8841-PMQL detected a parity
error, even if parity error handling is disabled in parity error
response (CFCS[6]).
30
Status
0
Signal System Error
When set, indicates that the KSZ8841-PMQL asserted the system
error SERR_N pin.
29
Status
0
Received Master Abort
When set, indicates that the KSZ8841-PMQL terminated a master
transaction with master abort.
28
Status
0
Received Target Abort
When set, indicates that the KSZ8841-PMQL master transaction
was terminated due to a target abort.
27
Status
0
Target Abort
This bit is set by KSZ8841-PMQL whenever it terminates with a
Target Abort. The CSR registers are all 32-bit Little Endian format.
For PCI register Read cycles, the KSZ8841-PMQL allows any
different combination of CBEN. For PCI register bus cycles, only
byte, word (16-bit), or Dword (32-bit) accesses are allowed. Any
other combination is illegal and is target aborted.
26 - 25
Status
01
Device Select Timing
Indicates the timing of the assertion of device select(DEVSEL_N).
These bits are fixed at 01, which indicates a medium assertion of
DEVSEL_N.
Category
Description
Value after hardware reset
0x884116C6
Write access rules
Write has no effect on the KSZ8841-PMQL.
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