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參數(shù)資料
| 型號(hào)： | PIC12F510_07 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8/14-Pin, 8-Bit Flash Microcontroller |
| 中文描述： | 8/14-Pin，8位閃存微控制器 |
| 文件頁數(shù)： | 68/116頁 |
| 文件大?。?/td> | 907K |
| 代理商： | PIC12F510_07 |
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PIC12F510/16F506
DS41268C-page 66
Preliminary
2007 Microchip Technology Inc.
10.5
Device Reset Timer (DRT)
On the PIC12F510/16F506 devices, the DRT runs any
time the device is powered up. DRT runs from Reset
and varies based on oscillator selection and Reset type
(see Table 10-6).
The DRT operates from a free running on-chip oscilla-
tor that is separate from INTOSC. The processor is
kept in Reset as long as the DRT is active. The DRT
delay allows V
DD
to rise above V
DD
minimum and for
the oscillator to stabilize.
Oscillator circuits, based on crystals or ceramic resona-
tors, require a certain time after power-up to establish
a stable oscillation. The on-chip DRT keeps the devices
in a Reset for a set period, as stated in Table 10-6, after
MCLR has reached a logic high (V
IH
MCLR) level.
Programming (GP3/RB3)/MCLR/V
PP
as MCLR and
using an external RC network connected to the MCLR
input is not required in most cases. This allows savings
in cost-sensitive and/or space restricted applications,
as well as allowing the use of the (GP3/RB3)/MCLR/
V
PP
pin as a general purpose input.
The DRT delays will vary from chip-to-chip due to V
DD
,
temperature
and
process
parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out, Wake-
up on Pin Change and Wake-up on Comparator
Change. See
Section 10.9.2 “Wake-up from Sleep
Reset”, Notes 1, 2 and 3
.
variation.
See
AC
10.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator that does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (GP5/RB5)/OSC1/CLKIN
pin and the internal 4/8 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a
SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration WDTE as a ‘
0
’ (see
Section 10.1 “Configuration Bits”
). Refer to the
PIC12F510/16F506 Programming Specifications to
determine how to access the Configuration Word.
TABLE 10-6:
TYPICAL DRT PERIODS
10.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms (with
no prescaler). If a longer time-out period is desired, a
prescaler with a divisor ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These
periods vary with temperature, V
DD
and part-to-part
process variations (see DC specs).
Under worst case conditions (V
DD
= Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
10.6.2
WDT PROGRAMMING
CONSIDERATIONS
The
CLRWDT
instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The
SLEEP
instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
Oscillator
Configuration
POR Reset
Subsequent
Resets
LP
18 ms
18 ms
XT
18 ms
18 ms
HS
(1)
18 ms
18 ms
EC
(1)
1.125 ms
10
μ
s
INTOSC
1.125 ms
10
μ
s
EXTRC
Note 1:
1.125 ms
10
μ
s
PIC16F506 only
Note:
It is the responsibility of the application
designer to ensure the use of the
1.125 ms nominal DRT will result in
acceptable operation. Refer to Electrical
Specifications for V
DD
rise time and
stability requirements for this mode of
operation.
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| PIC12F510-E/L | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8/14-Pin, 8-Bit Flash Microcontroller |
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| PIC12F510-E/MC | 功能描述:8位微控制器 -MCU 1.5 KB Flash 38 RAM 6 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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