參數(shù)資料
型號: PI7C8150BNDE
廠商: Pericom
文件頁數(shù): 97/109頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類型: 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 88 of 109
April 2009 – Revision 1.08
14.1.34
UPSTREAM (S TO P) MEMORY BASE REGISTER – OFFSET 50h
Bit
Function
Type
Description
3:0
64 bit addressing
R/O
0: 32 bit addressing
1: 64 bit addressing
Reset to 1
15:4
Upstream
Memory Base
Address
R/W
Controls upstream memory base address.
Reset to 00000000h
14.1.35
UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h
Bit
Function
Type
Description
19:16
64 bit addressing
R/O
0: 32 bit addressing
1: 64 bit addressing
Reset to 1
31:20
Upstream
Memory Limit
Address
R/W
Controls upstream memory limit address.
Reset to 000FFFFFh
14.1.36
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER
– OFFSET 54h
Bit
Function
Type
Description
31:0
Upstream
Memory Base
Address
R/W
Defines bits [63:32] of the upstream memory base
Reset to 0
14.1.37
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS
REGISTER – OFFSET 58h
Bit
Function
Type
Description
31:0
Upstream
Memory Limit
Address
R/W
Defines bits [63:32] of the upstream memory limit
Reset to 0
14.1.38
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
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