參數(shù)資料
型號(hào): PI7C8150BNDE
廠商: Pericom
文件頁數(shù): 85/109頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類型: 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 77 of 109
April 2009 – Revision 1.08
14.1.1
VENDOR ID REGISTER – OFFSET 00h
Bit
Function
Type
Description
15:0
Vendor ID
R/O
Identifies Pericom as vendor of this device. Hardwired as 12D8h.
14.1.2
DEVICE ID REGISTER – OFFSET 00h
Bit
Function
Type
Description
31:16
Device ID
R/O
Identifies this device as the PI7C8150B. Hardwired as 8150h.
14.1.3
COMMAND REGISTER – OFFSET 04h
Bit
Function
Type
Description
0
I/O Space Enable
R/W
Controls response to I/O access on the primary interface
0: ignore I/O transactions on the primary interface
1: enable response to I/O transactions on the primary interface
Reset to 0
1
Memory Space
Enable
R/W
Controls response to memory accesses on the primary interface
0: ignore memory transactions on the primary interface
1: enable response to memory transactions on the primary interface
Reset to 0
2
Bus Master
Enable
R/W
Controls ability to operate as a bus master on the primary interface
0: do not initiate memory or I/O transactions on the primary
interface and disable response to memory and I/O transactions on
the secondary interface
1: enables 7C8150 to operate as a master on the primary interfaces
for memory and I/O transactions forwarded from the secondary
interface
Reset to 0
3
Special Cycle
Enable
R/O
No special cycles defined.
Bit is defined as read only and returns 0 when read
4
Memory Write
And Invalidate
Enable
R/O
Memory write and invalidate not supported.
Bit is implemented as read only and returns 0 when read (unless
forwarding a transaction for another master)
5
VGA Palette
Snoop Enable
R/W
Controls response to VGA compatible palette accesses
0: ignore VGA palette accesses on the primary
1: enable positive decoding response to VGA palette writes on the
primary interface with I/O address bits AD[9:0] equal to 3C6h,
3C8h, and 3C9h (inclusive of ISA alias; AD[15:10] are not decoded
and may be any value)
6
Parity Error
Response
R/W
Controls response to parity errors
0: 7C8150 may ignore any parity errors that it detects and continue
normal operation
1: 7C8150 must take its normal action when a parity error is
detected
Reset to 0
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