參數(shù)資料
型號(hào)： PI7C8150BNDE
廠商： Pericom
文件頁數(shù)： 64/109頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 58 of 109
April 2009 – Revision 1.08
Primary
Data
Parity Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
0
Delayed Write
Upstream
Secondary
x / x
X = don’t care
Table 6-4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
The PI7C8150B must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
The S_PERR_L signal is detected asserted or a parity error is detected on the
secondary bus.
Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit
Secondary
Detected
Parity
Detected Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
0
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / 1
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
1
Posted Write
Downstream
Secondary
x / 1
0
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / 1
0
Delayed Write
Upstream
Primary
x / x
0
Delayed Write
Upstream
Secondary
x / x
X= don’t care
Table 6-5 shows assertion of P_PERR_L. This signal is set under the following
conditions:
PI7C8150B is either the target of a write transaction or the initiator of a read
transaction on the primary bus.
The parity-error-response bit must be set in the command register of primary interface.
PI7C8150B detects a data parity error on the primary bus or detects S_PERR_L
asserted during the completion phase of a downstream delayed write transaction on the
target (secondary) bus.
Table 6-5. Assertion of P_PERR_L
P_PERR_L
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
0 (asserted)
Read
Upstream
Primary
1 / x
相關(guān)PDF資料
PDF描述
V300A15E500B3 CONVERTER MOD DC/DC 15V 500W
DSPIC33FJ64MC202-E/MM IC DSPIC MCU/DSP 64K 28-QFN
PI7C8150AMAE IC PCI-PCI BRIDGE 2PORT 208-FQFP
PIC18F2515-I/SP IC MCU FLASH 24KX16 28-DIP
V300A15E500B2 CONVERTER MOD DC/DC 15V 500W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150BNDI 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BNDI-33 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BNDIE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BNDIE-33 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150DMAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*