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參數(shù)資料
| 型號： | PI7C8150A-33 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 5/115頁 |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150A-33 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 5 of 115
July 31, 2003 – Revision 1.031
TABLE OF CONTENTS
1
INTRODUCTION.............................................................................................................................. 11
2
SIGNAL DEFINITIONS ................................................................................................................... 12
2.1
S
IGNAL
T
YPES
............................................................................................................................... 12
2.2
S
IGNALS
........................................................................................................................................ 12
2.2.1
PRIMARY BUS INTERFACE SIGNALS
.......................................................................... 12
2.2.3
CLOCK SIGNALS
............................................................................................................... 15
2.2.4
MISCELLANEOUS SIGNALS
........................................................................................... 16
2.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS
........................................................ 17
2.2.6
JTAG BOUNDARY SCAN SIGNALS
................................................................................ 17
2.2.7
POWER AND GROUND
..................................................................................................... 18
2.3
PIN
LIST
–
208-PIN
FQFP........................................................................................................... 18
2.4
PIN
LIST
–
256-BALL
PBGA...................................................................................................... 20
PCI BUS OPERATION..................................................................................................................... 22
3.1
TYPES
OF
TRANSACTIONS..................................................................................................... 22
3.2
SINGLE
ADDRESS
PHASE........................................................................................................ 23
3.3
DEVICE
SELECT
(DEVSEL_L)
GENERATION....................................................................... 23
3.4
DATA
PHASE.............................................................................................................................. 23
3.5
WRITE
TRANSACTIONS .......................................................................................................... 23
3.5.1
MEMORY WRITE TRANSACTIONS
................................................................................ 24
3.5.2
MEMORY WRITE AND INVALIDATE
............................................................................ 25
3.5.3
DELAYED WRITE TRANSACTIONS
............................................................................... 25
3.5.4
WRITE TRANSACTION ADDRESS BOUNDARIES
....................................................... 26
3.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
..................................................... 26
3.5.6
FAST BACK-TO-BACK TRANSACTIONS
....................................................................... 27
3.6
READ
TRANSACTIONS............................................................................................................ 27
3.6.1
PREFETCHABLE READ TRANSACTIONS
.................................................................... 27
3.6.2
NON-PREFETCHABLE READ TRANSACTIONS
.......................................................... 27
3.6.3
READ PREFETCH ADDRESS BOUNDARIES
............................................................... 28
3.6.4
DELAYED READ REQUESTS
.......................................................................................... 29
3.6.5
DELAYED READ COMPLETION WITH TARGET
........................................................ 29
3.6.6
DELAYED READ COMPLETION ON INITIATOR BUS
................................................ 29
3.6.7
FAST BACK-TO-BACK READ TRANSACTION
............................................................. 30
3.7
CONFIGURATION
TRANSACTIONS...................................................................................... 30
3.7.1
TYPE 0 ACCESS TO PI7C8150B
....................................................................................... 31
3.7.2
TYPE 1 TO TYPE 0 CONVERSION
.................................................................................. 31
3.7.3
TYPE 1 TO TYPE 1 FORWARDING
................................................................................. 33
3.7.4
SPECIAL CYCLES
............................................................................................................. 34
3.8
TRANSACTION
TERMINATION.............................................................................................. 34
3.8.1
MASTER TERMINATION INITIATED BY PI7C8150B
................................................. 35
3.8.2
MASTER ABORT RECEIVED BY PI7C8150B
................................................................ 36
3.8.3
TARGET TERMINATION RECEIVED BY PI7C8150B
.................................................. 36
3.8.4
TARGET TERMINATION INITIATED BY PI7C8150B
.................................................. 41
ADDRESS DECODING..................................................................................................................... 43
4.1
ADDRESS
RANGES................................................................................................................... 43
4.2
I/O
ADDRESS
DECODING........................................................................................................ 43
4.2.1
I/O BASE AND LIMIT ADDRESS REGISTER
................................................................ 44
4.2.2
ISA MODE
........................................................................................................................... 45
3
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
| PI7C81552 | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C8152 | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
| PI7C8150AMAE | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150AMAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150AND | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-to-PCI BRIDGE |
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