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參數(shù)資料
| 型號： | PI7C8150A-33 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 17/115頁 |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150A-33 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 17 of 115
July 31, 2003 – Revision 1.031
CFG66 /
SCAN_EN_H /
CLK_RATE
125
K16
I
This is a multiplexed pin that has 3 functions (2 in
synchronous mode and 1 in asynchronous mode).
CFG66 - 66MHz Configuration (synchronous mode):
This pin is used to designate 66MHz operation. Tie
HIGH to enable 66MHz operation or tie LOW to
designate 33MHz operation.
SCAN_EN_H - Full-Scan Enable Control
(synchronous mode):
When SCAN_EN_H is LOW,
full-scan is in shift operation. When SCAN_EN_H is
HIGH, full-scan is in parallel operation.
Note: Valid only
in test mode. Pin is CFG66 in normal operation.
CLK_RATE – S_CLKOUT divider (asynchronous
mode):
Determines the S_CLKOUT frequency relation
to ASYNC_CLK_IN.
0: S_SCLKOUT is half the frequency of
ASYNC_CLK_IN.
1: S_CLKOUT is the same frequency as
ASYNC_CLK_IN.
Mode Selection:
Selector for Asynchronous or
Synchronous mode.
MS0
MS1
0
0
0
1
1
0
1
1
MS0, MS1
155, 106
B14, R16
I
Description
RESERVED
RESERVED
Synchronous Mode
Asynchronous Mode
2.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS
Name
GPIO[3:0]
Pin #
24, 25, 27, 28
Pin #
J3, J2, J1, K1
Type
TS
Description
General Purpose I/O Data Pins:
The 4 general-
purpose signals are programmable as either input-only
or bi-directional signals by writing the GPIO output
enable control register in the configuration space.
2.2.6
JTAG BOUNDARY SCAN SIGNALS
Name
TCK
Pin #
133
Pin #
H15
Type
I
Description
Test Clock.
Used to clock state information and data
into and out of the PI7C8150B during boundary scan.
Test Mode Select.
Used to control the state of the Test
Access Port controller.
Test Data Output.
When SCAN_EN_H is HIGH, it is
used (in conjunction with TCK) to shift data out of the
Test Access Port (TAP) in a serial bit stream.
Test Data Input.
When SCAN_EN_H is HIGH, it is
used (in conjunction with TCK) to shift data and
instructions into the Test Access Port (TAP) in a serial
bit stream.
Test Reset.
Active LOW signal to reset the Test Access
Port (TAP) controller into an initialized state.
TMS
132
H14
I
TDO
130
H16
O
TDI
129
J15
I
TRST_L
134
G15
I
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PDF描述 |
|---|---|
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
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| PI7C81552 | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
| PI7C8150AMAE | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150AMAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150AND | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-to-PCI BRIDGE |
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