
PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 81 of 115
July 31, 2003 – Revision 1.031
14
CONFIGURATION REGISTERS
PCI configuration defines a 64-byte space (configuration header) to define various
attributes of PI7C8150B as shown below.
14.1
CONFIGURATION REGISTER
31-24
23-16
15-8
7-0
Address
00h
04h
08h
0Ch
10h
14h
18h
Device ID
Primary Status
Vendor ID
Command
Class Code
Header Type
Revision ID
Cache Line Size
Reserved
Primary Latency Timer
Reserved
Reserved
Secondary Bus
Number
I/O Limit
Secondary Latency
Timer
Subordinate Bus
Number
Primary Bus Number
Secondary Status
Memory Limit
Prefetchable Memory Limit
I/O Base
1Ch
20h
24h
28h
2Ch
30h
34h
Memory Base
Prefetchable Memory Base
Prefetchable Base Upper 32-bit
Prefetchable Limit Upper 32-bit
I/O Limit Upper 16-bit
I/O Base Upper 16-bit
Reserved
Capability Pointer to
DCh
Reserved
38h
3Ch
40h
44h
48h
4Ch
Bridge Control
Arbiter Control
Reserved
Diagnostic / Chip Control
Interrupt Line
Reserved
Upstream Memory Control
Extended Chip Control
Secondary
Bus Arbiter
Preemption
Control
Hot Swap Switch Time Slot
Upstream (S to P) Memory Limit
Upstream (S to P) Memory Base
50h
54h
58h
5Ch
60h
64h
Upstream (S to P) Memory Base Upper 32-bit
Upstream (S to P) Memory Limit Upper 32-bit
Reserved
Reserved
GPIO Data and Control
P_SERR# Event
Disable
Reserved
P_SERR_L Status
Secondary Clock Control
68h
6Ch
70h
74h
78h
7Ch
80h
Reserved
Reserved
Reserved
Port Option
Retry Counter
Reserved
Secondary Master Timeout Counter
Primary Master Timeout Counter
Reserved
84h-AFh
B0h
B4h-D8h
DCh
E0h
E4h
E8h-FFh
Chassis Number
Slot Number
Next Pointer
Capability ID
Reserved
Power Management Capabilities
Reserved
Reserved
Next Item Pointer
Capability ID
PPB Support Extensions
Power Management Data
Next Pointer
Capability ID
Reserved