
PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 73 of 115
July 31, 2003 – Revision 1.031
PI7C8150B-33 can be run in the following frequency configuration:
Primary (MHz)
25MHz to 33MHz
To set asynchronous mode support, MS0 and MS1 must be configured accordingly:
MS0
MS1
0
0
1
1
When MS0 and MS1 are pulled to HIGH during the deassertion of P_RST, PI7C8150B
will go into asynchronous mode. The secondary clock outputs will then be derived from
ASYNC_CLKIN and not P_CLK. S_CLKOUT[9] is still connected to S_CLKIN to
provide the same timing as the bus clocks. CFG66/SCAN_EN_H becomes CLK_RATE in
asynchronous mode. Pulling CLK_RATE HIGH sets S_CLKOUT[9:0] equal to
ASYNC_CLKIN. Pulling CLK_RATE LOW sets S_CLKOUT[9:0] to half the frequency
of ASYNC_CLKIN. PI7C8150B will not be able to drive S_M66EN in asynchronous
mode.
Secondary (MHz)
25MHz to 33MHz
Description
0
1
0
1
Reserved for future use
Reserved for future use
Synchronous Mode
Asynchronous Mode
10
GENERAL PURPOSE I/O INTERFACE
The PI7C8150B implements a 4-pin general purpose I/O interface. During normal
operation, device specific configuration registers control the GPIO interface. The GPIO
interface can be used for the following functions:
!
During secondary interface reset, the GPIO interface can be used to shift in a 16-bit
serial stream that serves as a secondary bus clock disable mask.
!
Along with the GPIO[3] pin, a live insertion bit can be used to bring the PI7C8150B to
a halt through hardware, permitting live insertion of option cards behind the
PI7C8150B.
10.1
GPIO CONTROL REGISTERS
During normal operation, the following device specific configuration registers control the
GPIO interface:
!
The GPIO output data register
!
The GPIO output enable control register
!
The GPIO input data register
These registers consist of five 8-bit fields:
!
Write-1-to-set output data field