參數(shù)資料
型號(hào): PI74SSTU32866NBE
廠商: Pericom
文件頁(yè)數(shù): 6/18頁(yè)
文件大?。?/td> 0K
描述: IC 25BIT CONFIG REG BUFF 96LFBGA
產(chǎn)品變化通告: Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝: 285
邏輯類(lèi)型: 帶奇偶位的可配置寄存緩沖器
位數(shù): 25
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 96-LFBGA
供應(yīng)商設(shè)備封裝: 96-LFBGA(13.5x5.5)
包裝: 托盤(pán)
14
PS8739B
11/21/05
PI74SSTU32866
25-bit 1:1 or 14-bit 1:2 Configurable
Registered Buffer with Parity
Notes:
17. Includes 350ps test load transmission-line delay.
18. This parameter is not necessarily production tested.
Switching Characteristics Over Recommended Operating Free Air Temperature range (See Figure 1)
Notes:
19. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
Data Output Edge Rates Over Recommended Operating Free Air Temperature range (See Figure 2)
Symbol
Parameter
Measurement Condtions
Min. Max. Units
dV/dt_r
Rising edge slew rate
From 20% to 80%
1
4
V/ns
dV/dt_f
Falling edge slew rate
From 20% to 80%
1
4
dV/dt_(19)
absolute difference between dV/dt_r and dV/dt_f
From 20% or 80% to 80% or 20%
1
Symbol
Parameter
Measure Condition
Min.
Max. Units
fMAX
Maximum input clock frequency
270
MHz
tPDM
Propagation Delay, single bit switching
From CK↑ and CK↓ to Qn
1.41
2.15
ns
tPDMS(17,18) Propagation Delay Simultaneous
Switching
2.35
ns
tPD
Propagation Delay
From CK↑ and CK↓ to PPO
0.5
1.8
ns
tLH
Low-to-High propagation delay
From CK↑ and CK↓ to QERR
1.2
3
ns
tHL
High-to-Low propagation delay
1
2.4
ns
tPHL
High-to-Low propagation delay
From RST↓ to Qn↓
3
ns
tPHL
High-to-Low propagation delay
From RST↓ to PPO↓
3
ns
tPLH
Low-to-high propagation delay
From RST↓ to QERR↓
3
ns
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