參數(shù)資料
型號: PI74SSTU32866NBE
廠商: Pericom
文件頁數(shù): 14/18頁
文件大?。?/td> 0K
描述: IC 25BIT CONFIG REG BUFF 96LFBGA
產(chǎn)品變化通告: Product Discontinuation Notice 22/Jan/2010
標準包裝: 285
邏輯類型: 帶奇偶位的可配置寄存緩沖器
位數(shù): 25
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 96-LFBGA
供應商設備封裝: 96-LFBGA(13.5x5.5)
包裝: 托盤
5
PS8739B
11/21/05
PI74SSTU32866
25-bit 1:1 or 14-bit 1:2 Configurable
Registered Buffer with Parity
Name
Description
Characteristics
GND
Ground
Ground Input
VDD
Power Supply
1.8V nominal
VREF
Input Reference Voltage
0.9V nominal
CK
Positive master clock input
Differential Clock input
CK
Negative master clock input
Differential Clock input
C0, C1
Configuration control inputs
LVCMOS inputs
RST
Asynchronous reset input - resets registers and disables VREF data and clock differen-
tial - input receivers
LVCMOS inputs
CSR, DCS Chip select inputs disables D1-D25 outputs switching when both inputs are high(5)
SSTL_18 input
D1-D25
Data input - clocked in on the crossing of the rising edge of CK and the falling edge
of CK
SSTL_18 input
DODT
The outputs of this register bit will not be suspended by the DCS and CSR control
SSTL_18 input
PAR_IN
Parity input - arrives one clock cycle after the corresponding data input
SSTL_18 input
DCKE
The outputs of this register bit will not be suspended by the DCS and CSR control
SSTL_18 input
Q1-Q25
Data outputs that are suspended by the DCS and CSR control(6)
1.8V CMOS output
PPO
Partial Parity out - indicates odd parity of inputs D1- D25(5)
1.8V CMOS output
QCS
Data output that will not be suspended by the DCS and CSR control
1.8V CMOS output
QODT
Data output that will not be suspended by the DCS and CSR control
1.8V CMOS output
QCKE
Data output that will not be suspended by the DCS and CSR control
1.8V CMOS output
QERR
Output error bit - generated one clock cycle after the corresponding data output
Open-drain output
NC
No internal connection
DNU
Do not use - inputs are in stand-by-equivalent mode and outputs are driven low
Terminal Functions
Notes:
5.
Data inputs = D2, D3, D5, D6, D8-D25 when C0=0 and C1=0
Data inputs = D2, D3, D5, D6, D8-D14 when C0=0 and C1=1
Data inputs = D1-D6, D8-D10, D12, D13 when C0=1 and C1=1
6.
Data outputs = Q2, Q3, Q5, Q6, Q8-Q25 when C0=0 and C1=0
Data outputs = Q2, Q3, Q5, Q6, Q8-Q14 when C0=0 and C1=1
Data outputs = Q1-Q6, Q8-Q10, Q12, Q13 when C0=1 and C1=1
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