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參數(shù)資料
| 型號： | PI74SSTVF16859AZBE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REG BUFFER 13-26BIT 56-QFN |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 11/Feb/2008 |
| 標準包裝： | 348 |
| 系列： | 74SSTVF |
| 邏輯類型： | 13 位至 26 位寄存緩沖器，DDR |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 位數(shù)： | 13，26 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-QFN-EP（8x8） |
| 包裝： | 托盤 |
1
PS8684B
10/30/06
Product Description
Pericom Semiconductor’s PI74SSTVF16859A logic circuit is
produced using the Company’s advanced sub-micron CMOS
technology, achieving industry leading speed.
All inputs are compatible with the JEDEC standard for SSTL_2,
except the LVCMOS reset (RESET) input. All outputs are SSTL_2,
Class II compatible.
The device operates from a differential clock (CLK and CLK). Data
registered at the crossing of CLK going HIGH, and CLK going LOW.
The PI74SSTVF16859A supports low-power standby operation.
When RESET is LOW, the differential input receivers are disabled,
and undriven (floating) data, clock and reference voltage (VREF)
inputs are allowed. In addition, when RESET is LOW, all registers are
reset, and all outputs are forced LOW. The LVCMOS RESET input
must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock
has been supplied, RESET must be held in the LOW state during
power up.
In the DDR DIMM application, RESET is specified to be completely
asynchronous with respect to CLK and CLK. Therefore, no timing
relationship can be guaranteed between the two. When entering
RESET, the register will be cleared and the outputs will be driven
LOW quickly, relative to the time to disable the differential input
receivers, thus ensuring no glitches on the output. However, when
coming out of RESET, the register will become active quickly, relative
to the time to enable the differential input receivers. When the data
inputs are LOW, and the clock is stable, during the time from the
LOW-to-HIGH transition of RESET until the input receivers
are fully enabled, the design must ensure that the outputs will
remainLOW.
Pericom’s PI74SSTVF16859A is characterized for operation from
0°C to 70°C.
Product Features
PI74 SSTVF16859A is designed for low-voltage operation,
2.5V for PC1600 ~ PC2700; 2.6V for PC3200
Supports SSTL_2 Class I specifications on outputs
All Inputs are SSTL_2 Compatible, except RESET
which is LVCMOS.
Designed for DDR Memory
Flow-Through Architecture
Package: 56-pin, Plastic Very Thin Fine Pitch Quad Flat No-
Lead QFN (ZB). (Pb-free available)
Product Pin Description
13-Bit to 26-Bit Registered Buffer
Logic Block Diagram
TO 12 OTHER CHANNELS
RESET
CLK
35
36
VREF
D1
24
32
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CLK
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7
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↓ = Transition HIGH-to-LOW
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PI74SSTVF16859A
06-0288
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