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參數(shù)資料
| 型號(hào)： | PI74SSTU32866NBE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 25BIT CONFIG REG BUFF 96LFBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 285 |
| 邏輯類型： | 帶奇偶位的可配置寄存緩沖器 |
| 位數(shù)： | 25 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 96-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 96-LFBGA（13.5x5.5） |
| 包裝： | 托盤 |
2
PS8739B
11/21/05
PI74SSTU32866
25-bit 1:1 or 14-bit 1:2 Configurable
Registered Buffer with Parity
no timing relationship can be guaranteed between the two. When
entering reset, the register will be cleared and the Qn outputs
will be driven low quickly, relative to the time to disable the
differential input receivers. However, when coming out of reset,
the register will become active quickly, relative to the time to
enable the differential input receivers. As long as the data inputs
are low, and the clock is stable during the time from the low-to-
high transition of RST until the input receivers are fully enabled,
the design of the PI74SSTU32866 must ensure that the outputs
will remain low, thus ensuring no glitches on the output.
To ensure defined outputs from the register before a stable clock
has been supplied, RST must be held in the low state during
power up.
The device supports low-power standby operation. When RST
is low, the differential input receivers are disabled, and undriven
(floating) data, clock and reference voltage (VREF) inputs are
allowed. In addition, when RST is low all registers are reset, and
all outputs are forced low. The LVCMOS RST, C0, and C1 inputs
must always be held at a valid logic high or low level.
The device also supports low-power active operation by
monitoring both system chip select (DCS and CSR) inputs and
will gate the Qn and PPO outputs from changing states when both
DCS and CSR inputs are high. If either DCS or CSR input is low,
the Qn and PPO outputs will function normally. The RST input
has priority over the DCS and CSR control and when driven low
will force the Qn and PPO outputs low, and the QERR output
high. If the DCS control functionality is not desired, then the CSR
input can be hard-wired to ground, in which case, the setup-time
requirement for DCS would be the same as for the other D data
inputs. To control the low-power mode with DCS only, then the
CSR input should be pulled up to VDD through a pullup resistor.
Product Description - Continued
96-ball LFBGA (MO-205CC)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI74SSTU32866NBEX | 功能描述:寄存器 25B 1:1 or 14B 1:2 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| PI74SSTV16857AE | 功能描述:寄存器 14Bit Lead Free Register Buffer RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| PI74SSTV16857AEX | 功能描述:寄存器 14Bit Lead Free Register Buffer RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| PI74SSTV16859A | 制造商:Pericom Semiconductor Corporation 功能描述:Registered Buffer Single 13-CH CMOS 64-Pin TSSOP Tube |
| PI74SSTV16859AE | 制造商:Pericom Semiconductor Corporation 功能描述:Registered Buffer Single 13-CH CMOS 64-Pin TSSOP Tube 制造商:Pericom Semiconductor Corporation 功能描述:13 to 26 Bit 2.3 to 2.7 V 2.8 ns Surface Mount Registered Buffer - TSSOP-64 |
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