參數(shù)資料
型號(hào): PI2EQX5904NJE
廠商: Pericom
文件頁(yè)數(shù): 5/23頁(yè)
文件大?。?/td> 0K
描述: IC PCIE 2.0 REDRIVER 100LBGA
標(biāo)準(zhǔn)包裝: 1
系列: PCI Express®(PCIe), ReDriver™
類型: 轉(zhuǎn)接驅(qū)動(dòng)器
驅(qū)動(dòng)器/接收器數(shù): 2/2
規(guī)程: PCIe? 2.0
電源電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 100-BGA
供應(yīng)商設(shè)備封裝: 100-LBGA(11x11)
包裝: 托盤
13
www.pericom.com
PS-0.5
10/18/10
All trademarks are property of their respective owners.
PI2EQX5904
5.0Gbps 4-Lane PCIe 2.0 ReDriver with Equalization & Emphasis
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
1
0
Name
PD_A0#
PD_B0#
PD_A1#
PD_B1#
PD_A2#
PD_B2#
PD_A3#
PD_B3#
Type
R/W
Power-on
State
PD#
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Power Down Control register allows for individual control over each channel for power savings. When
PD_xy# is logic 0 the channel is turned off. When PD_xy# is 1 then the channel is enabled for normal
operation.
BYTE 7 - Receiver Detect Enable (RXD)
RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
1
0
Name
RXD_A0
RXD_B0
RXD_A1
RXD_B1
RXD_A2
RXD_B2
RXD_A3
RXD_B3
Type
R/W
Power-on
State
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual channel. When
RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1, then the receiver detect state machine is
enabled for operation. The initial state of the register bits are determined by the RXD_A and RXD_B input pins during power-up.
BYTE 8 - A-Channels Equalizer and Output Control (AEOC)
SELx_A: Equalizer configuration, Dx_A: Emphasis control, Sx_A: Output level control (see Configuration Table)
Bit
7
6
5
4
3
2
1
0
Name
SEL0_A
SEL1_A
SEL2_A
D0_A
D1_A
D2_A
S0_A
S1_A
Type
R/W
Power-on
State
SEL0_A
SEL1_A
SEL2_A
D0_A
D1_A
D2_A
S0_A
S1_A
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The A-Channels Equalizer and Output Control register is used to control the configuration of the input equalizer and output
emphasis and levels of the four A channels. These register bits are loaded from the input configuration pins of the same name at
power-on. These bits may be changed if the MODE# input is set to allow I2C configuration. Please refer to the tables (1) Equalizer
Configuration, (2) Output Swing Configuration and
10-0217
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