參數(shù)資料
型號(hào): PI2EQX5904NJE
廠商: Pericom
文件頁(yè)數(shù): 10/23頁(yè)
文件大?。?/td> 0K
描述: IC PCIE 2.0 REDRIVER 100LBGA
標(biāo)準(zhǔn)包裝: 1
系列: PCI Express®(PCIe), ReDriver™
類型: 轉(zhuǎn)接驅(qū)動(dòng)器
驅(qū)動(dòng)器/接收器數(shù): 2/2
規(guī)程: PCIe? 2.0
電源電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 100-BGA
供應(yīng)商設(shè)備封裝: 100-LBGA(11x11)
包裝: 托盤(pán)
18
www.pericom.com
PS-0.5
10/18/10
All trademarks are property of their respective owners.
PI2EQX5904
5.0Gbps 4-Lane PCIe 2.0 ReDriver with Equalization & Emphasis
Equalizer
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
JRS-T
Residual jitter
Total
0.3
Ulp-p
JRS-D
Residual jitter
Deterministic
0.2
Ulp-p
JRM
Random jitter
Note 2
1.5
psrms
Notes
1. K28.7 pattern is applied differentially at point A as shown in AC test circuit (see figure).
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter.
Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Re-
sidual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must
be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of the AC test circuit (see figure).
CML Transmitter Output
Symbol
Parameter
Conditions
Min. Typ.
Max.
Units
ZOUT
Output resistance
Single ended
40
50
60
Ohms
ZTX-DIFF-DC
DC Differential TX Imped-
ance
80
100
120
VDIFFP
Output Voltage Swing, Dif-
ferential
|VTX-D+ - VTX-D-|
200
800
mVp-p
VTX-DIFFP-P
Differential Peak-to-peak
Ouput Voltage
VTX-DIFFP-P = 2 * | VTX-D+ -
VTX-D- |
0.4
1.6
V
VTX-C
Common-Mode Voltage
| VTX-D+ + VTX-D- | / 2
VDD- 0.3
tF, tR
Transition Time
20% to 80%
150
ps
CTX(1)
AC Coupling Capacitor
75
200
nF
Note:
1. Recommended external blocking capacitor.
SDA and SCL I/O for I2C-bus
Symbol
Parameter
Conditions Min.
Typ.
Max.
Units
VIH
DC input logic high
0.85VDD
3.6
V
VIL
DC input logic low
-0.3
0.3VDD
VOL
DC output logic low
IOL = 3mA
0.4
Vhys
Hysteresis of Schmitt trigger input
0.2
(VDD = 1.2V ± 0.05V, TA = 0 to 70°C)
(VDD = 1.2 ± 0.05v, TA = 0 to 70°C)
10-0217
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