參數(shù)資料
型號: PI2EQX5904NJE
廠商: Pericom
文件頁數(shù): 3/23頁
文件大小: 0K
描述: IC PCIE 2.0 REDRIVER 100LBGA
標(biāo)準(zhǔn)包裝: 1
系列: PCI Express®(PCIe), ReDriver™
類型: 轉(zhuǎn)接驅(qū)動器
驅(qū)動器/接收器數(shù): 2/2
規(guī)程: PCIe? 2.0
電源電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 100-BGA
供應(yīng)商設(shè)備封裝: 100-LBGA(11x11)
包裝: 托盤
11
www.pericom.com
PS-0.5
10/18/10
All trademarks are property of their respective owners.
PI2EQX5904
5.0Gbps 4-Lane PCIe 2.0 ReDriver with Equalization & Emphasis
Register Description
Byte 0 - Signal Detect (SIG)
SIG_xy=0=low input signal, SIG_xy=1=valid input signal
Bit
7
6
5
4
3
2
1
0
Name
SIG_A0
SIG_B0
SIG_A1
SIG_B1
SIG_A2
SIG_B2
SIG_A3
SIG_B3
Type
R
Power-on
State
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Signal Detect register provides information on the instantaneous status of the channel input from the Input Level Threshold
Detect circuit. If the input level falls below the Vth- level the relevant SIG_xy bit will be 0, indicating a low-level noise or electri-
cal idle input, resulting in the outputs going to the high-impedance off state or squelch mode. If the input level is above Vth-, then
SIG_xy is 1, indicating a valid input signal, and active signal recovery operation.
Byte 1 - Receiver Detect Output Register (RX50)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis
Bit
7
6
5
4
3
2
1
0
Name
RX50_A0
RX50_B0
RX50_A1
RX50_B1
RX50_A2
RX50_B2
RX50_A3
RX50_B3
Type
R
Power-on
State
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The RX50_xy bits report the result of a receiver detection cycle. One bit is assigned for each channel of the device. RX50_xy is at a
logic 1 level indicating a load and receiver was detected. When RX50_xy is 0 then a load device was not detected. The RX50 regis-
ter is read-only, and is undefined after power-up until a Receiver Detection cycle completes.
Byte 2 - Loopback and Emphasis Control Register (LBEC)
LB_xyxy#=0=loopback mode, LB_xyxy#=1=normal mode, DE_x=0=pre-emphasis, DE_x=1=de-emphasis
Bit
7
6
5
4
3
2
1
0
Name
LB_A0B0#
LB_A1B1#
LB_A2B2#
LB_A3B3#
DE_A
DE_B
rsvd
Type
R/W
R
Power-on
State
LB#
DE_A
DE_B
X
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
Individual control for each lane is provided for the loopback function via this register.
10-0217
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