參數(shù)資料
型號(hào)： PHP130N03LT
廠商： NXP SEMICONDUCTORS
元件分類： JFETs
英文描述： TrenchMOS transistor Logic level FET
中文描述： 75 A, 30 V, 0.006 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB
封裝： PLASTIC, TO-220AB, 3 PIN
文件頁數(shù)： 1/6頁
文件大?。?/td> 51K
代理商： PHP130N03LT
Philips Semiconductors
Product specification
TrenchMOS
transistor
Logic level FET
PHP130N03LT, PHB130N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
V
DSS
= 30 V
’Trench’
technology
Very low on-state resistance
Fast switching
Stable off-state characteristics
High thermal cycling performance
Low thermal resistance
I
D
= 75 A
R
DS(ON)
≤
6 m
(V
GS
= 5 V)
R
DS(ON)
≤
5 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’
trench
’ technology.
Thedevice has very low on-state resistance. Itis intended for use in dcto dc converters and general purpose switching
applications.
The PHP130N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB130N03LT is supplied in the SOT404 surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
Drain-source voltage
V
DGR
Drain-gate voltage
V
GS
Gate-source voltage
I
D
Continuous drain current
CONDITIONS
T
j
= 25 C to 175C
T
j
= 25 C to 175C; R
GS
= 20 k
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
±
13
75
75
240
187
175
UNIT
V
V
V
A
A
A
W
C
T
mb
= 25 C; V
GS
= 5 V
T
mb
= 100 C; V
GS
= 5 V
T
mb
= 25 C
T
mb
= 25 C
I
DM
P
D
T
j
, T
stg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
d
g
s
1
3
tab
2
1 2 3
tab
1
It is not possible to make connection to pin 2 of the SOT404 package.
January 1998
1
Rev 1.300
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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