參數(shù)資料
型號(hào)： PHN205
廠商： NXP SEMICONDUCTORS
元件分類： 小信號(hào)晶體管
英文描述： Dual N-channel enhancement mode MOS transistor
中文描述： 6400 mA, 30 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MS-012AA
封裝： PLASTIC, SO-8
文件頁數(shù)： 5/12頁
文件大?。?/td> 88K
代理商： PHN205
1997 Oct 22
5
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
CHARACTERISTICS
T
j
= 25
°
C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Per N-channel
V
(BR)DSS
V
GSth
I
DSS
I
GSS
R
DSon
drain-source breakdown voltage
gate-source threshold voltage
drain-source leakage current
gate leakage current
drain-source on-state resistance
V
GS
= 0; I
D
= 10
μ
A
V
GS
= V
DS
; I
D
= 1 mA
V
GS
= 0; V
DS
= 24 V
V
GS
=
±
20 V; V
DS
= 0
V
GS
= 4.5 V; I
D
= 1.6 A
V
GS
= 10 V; I
D
= 3.2 A
V
GS
= 0; V
DS
= 24 V; f = 1 MHz
V
GS
= 0; V
DS
= 24 V; f = 1 MHz
V
GS
= 0; V
DS
= 24 V; f = 1 MHz
V
GS
= 10 V; V
DD
= 15 V; I
D
= 3.2 A
V
GS
= 10 V; V
DD
= 15 V; I
D
= 3.2 A
V
GS
= 10 V; V
DD
= 15 V; I
D
= 3.2 A
V
GS
= 0 to 10 V; V
DD
= 15 V;
I
D
= 1 A; R
gen
= 6
; see Fig.4
V
GS
= 0 to 10 V; V
DD
= 15 V;
I
D
= 1 A; R
gen
= 6
; see Fig.4
V
GS
= 0 to 10 V; V
DD
= 15 V;
I
D
= 1 A; R
gen
= 6
; see Fig.4
V
GS
= 10 to 0 V; V
DD
= 15 V;
I
D
= 1 A; R
gen
= 6
; see Fig.4
V
GS
= 10 to 0 V; V
DD
= 15 V;
I
D
= 1 A; R
gen
= 6
; see Fig.4
V
GS
= 10 to 0 V; V
DD
= 15 V;
I
D
= 1 A; R
gen
= 6
; see Fig.4
30
1
450
200
100
15
1
5
7
2.8
100
±
100
0.1
0.05
V
V
nA
nA
pF
pF
pF
nC
nC
nC
ns
C
iss
C
oss
C
rss
Q
G
Q
GS
Q
GD
t
d(on)
input capacitance
output capacitance
reverse transfer capacitance
total gate charge
gate-source charge
gate-drain charge
turn-on delay time
t
f
fall time
8
ns
t
on
turn-on switching time
15
ns
t
d(off)
turn-off delay time
20
ns
t
r
rise time
12
ns
t
off
turn-off switching time
32
ns
Source-drain diode
V
SD
source-drain diode forward
voltage
reverse recovery time
V
GD
= 0; I
S
= 1.25 A
1
V
t
rr
I
S
= 1.25 A; di/dt =
100 A/
μ
s
45
ns
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