參數(shù)資料
型號： PHD11N03LT
廠商： NXP SEMICONDUCTORS
元件分類： JFETs
英文描述： N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應(yīng)管)
中文描述： 10.3 A, 30 V, 0.15 ohm, N-CHANNEL, Si, POWER, MOSFET
封裝： PLASTIC, DPAK-3
文件頁數(shù)： 7/11頁
文件大?。?/td> 105K
代理商： PHD11N03LT
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
Logic level FET
PHB11N03LT, PHD11N03LT
MECHANICAL DATA
Fig.16. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
UNIT
A
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
A1
D1
D
max.
E
e
Lp
HD
Q
c
2.54
2.60
2.20
15.40
14.80
2.90
2.10
11
1.60
1.20
10.30
9.70
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
b
DIMENSIONS (mm are the original dimensions)
SOT404
0
2.5
5 mm
scale
Plastic single-ended surface mounted package (Philips version of D
2
-PAK); 3 leads
(one lead cropped)
SOT404
e
e
E
b
D1
HD
D
Q
Lp
c
A1
A
1
3
2
mounting
base
98-12-14
99-06-25
September 1999
7
Rev 1.000
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PHD11N06LT 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:N-channel TrenchMOS transistor Logic level FET
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