參數(shù)資料
型號： PHD11N03LT
廠商： NXP SEMICONDUCTORS
元件分類： JFETs
英文描述： N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應(yīng)管)
中文描述： 10.3 A, 30 V, 0.15 ohm, N-CHANNEL, Si, POWER, MOSFET
封裝： PLASTIC, DPAK-3
文件頁數(shù)： 2/11頁
文件大小： 105K
代理商： PHD11N03LT
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
Logic level FET
PHB11N03LT, PHD11N03LT
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
Non-repetitive avalanche
energy
CONDITIONS
Unclamped inductive load, I
= 3.3 A;
t
p
= 220
μ
s; T
j
prior to avalanche = 25C;
V
≤
15 V; R
GS
= 50
; V
GS
= 5 V; refer to
fig:15
MIN.
-
MAX.
25
UNIT
mJ
I
AS
Peak non-repetitive
avalanche current
-
10.3
A
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
Thermal resistance junction
to mounting base
R
th j-a
Thermal resistance junction
to ambient
CONDITIONS
TYP.
-
MAX.
4.5
UNIT
K/W
SOT428 and SOT404 package, pcb
mounted, minimum footprint
50
-
K/W
ELECTRICAL CHARACTERISTICS
T
j
= 25C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
Drain-source breakdown
voltage
V
GS(TO)
Gate threshold voltage
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
MIN.
30
26
1.0
0.5
-
-
-
-
4
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
-
-
1.5
2.0
-
-
-
2.3
100
130
120
150
250
315
7
-
10
100
0.05
10
-
500
3.8
-
1.2
-
1.7
-
6
16
64
80
20
30
26
40
3.5
-
4.5
-
V
V
V
V
V
T
j
= -55C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175C
T
j
= -55C
R
DS(ON)
Drain-source on-state
resistance
V
GS
= 10 V; I
= 5.5 A
V
GS
= 5 V; I
D
= 5.5 A
m
m
m
S
nA
μ
A
μ
A
nC
nC
nC
ns
ns
ns
ns
nH
nH
T
j
= 175C
g
fs
I
GSS
I
DSS
Forward transconductance
Gate source leakage current V
GS
=
±
5 V; V
DS
= 0 V
Zero gate voltage drain
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
V
DS
= 25 V; I
D
= 5.5 A
V
DS
= 30 V; V
GS
= 0 V;
T
j
= 175C
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
I
D
= 10 A; V
DD
= 15 V; V
GS
= 5 V
V
DD
= 30 V; R
D
= 2.7
;
R
= 10
; V
GS
= 5 V
Resistive load
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
L
s
Internal source inductance
-
7.5
-
nH
C
iss
C
oss
C
rss
Input capacitance
Output capacitance
Feedback capacitance
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
-
-
-
250
55
42
330
75
55
pF
pF
pF
September 1999
2
Rev 1.000
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參數(shù)描述
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