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參數(shù)資料
| 型號： | PHD11N03LT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | N-channel TrenchMOS transistor Logic level FET(N溝道TrenchMOS 晶體管邏輯電平場效應(yīng)管) |
| 中文描述： | 10.3 A, 30 V, 0.15 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | PLASTIC, DPAK-3 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 105K |
| 代理商： | PHD11N03LT |
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
Logic level FET
PHB11N03LT, PHD11N03LT
Fig.1. Normalised power dissipation.
PD% = 100
P
D
/P
D 25 C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
I
D
/I
D 25 C
= f(T
mb
); conditions: V
GS
≥
5 V
Fig.3. Safe operating area. T
= 25 C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Fig.5. Typical output characteristics, T
j
= 25 C
I
D
= f(V
DS
)
Fig.6. Typical on-state resistance, T
j
= 25 C
R
DS(ON)
= f(I
D
)
Normalised Power Derating, PD (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
0.1
1
10
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
single pulse
D = 0.5
0.2
0.1
0.05
0.02
tp
D = tp/T
D
P
T
Normalised Current Derating, ID (%)
0
10
20
30
40
50
60
70
80
90
100
0
25
50
75
100
125
150
175
Mounting Base temperature, Tmb (C)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0.2
0.4
0.6
Drain-Source Voltage, VDS (V)
0.8
1
1.2
1.4
1.6
1.8
2
Drain Current, ID (A)
2.8 V
2.6 V
Tj = 25 C
VGS = 10V
3 V
3.2 V
3.4 V
2.4 V
5 V
0.1
1
10
100
1
10
100
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
D.C.
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
1
2
3
5
6
7
8
9
10
11
Dr4
Drain-Source On Resistance, RDS(on) (Ohms)
VGS = 10V
Tj = 25 C
3.2 V
5 V
3.4 V
3 V
2.8V
2.6 V
2.4 V
September 1999
4
Rev 1.000
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