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參數(shù)資料
| 型號(hào)： | PEB2466-H |
| 英文描述： | LTC3409 Evaluation Kit |
| 中文描述： | A-Law/u-Law編解碼器 |
| 文件頁(yè)數(shù)： | 39/73頁(yè) |
| 文件大?。?/td> | 1618K |
| 代理商： | PEB2466-H |
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PEB 2466
PEF 2466
Interface Description
Hardware Reference Manual
30
2001-02-20
5.2
PCM Interface
The SICOFI
4-μC provides an industry
–
standard PCM Interface with access to two PCM
highways. The PCM Interface has the following features:
Data rate from 128 kbit/s to 8 Mbit/s per highway,
2 to 128 time slots per frame per highway,
PCM data format serialized 8 bits with MSB first,
Configurable A-Law or μ-Law coding,
Independently configurable time slot and highway for each channel and direction,
PCM clock speed of once or twice the bit rates,
Programmable sampling slopes, and
Programmable frame delay.
5.2.1
PCM Interface Pins
Table 22
PCM Interface Pins
5.2.2
Figure 17
and
Figure 18
illustrate the time slot and bit positions resulting from the
programming example below:
PCM Receive and Transmit Example
Symbol
PCLK
FSC
DRA
DRB
DXA
DXB
TCA#
TCB#
Pin
32
31
27
30
26
29
25
28
Function
PCM-Clock, 128 kHz to 8192 kHz; shared for both highways.
Frame Synchronization Clock, 8 kHz; shared for both highways.
Receive Data input for PCM-highway A.
Receive Data input for PCM-highway B.
Transmit Data output for PCM-highway A, open drain.
Transmit Data output for PCM-highway B, open drain.
Transmit Control output for highway A, low when DXA is active.
Transmit Control output for highway B, low when DXB is active.
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