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參數(shù)資料
| 型號： | PE3293 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis |
| 中文描述： | 1.8GHz/550MHz雙分?jǐn)?shù)N超低的雜散鎖相環(huán)頻率合成 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 266K |
| 代理商： | PE3293 |
PE3293
Product Specification
Table 7. AC Characteristics
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 7 of 18
V
DD
= 3.0 V, -40
°
C < T
A
< 85
°
C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Latches (see figure 6)
f
Clock
Serial data clock frequency
10
MHz
t
ClockH
Serial clock HIGH time
50
ns
t
ClockL
Serial clock LOW time
50
ns
t
DSU
Data set-up time to Clock rising edge
50
ns
t
DHLD
Data hold time after Clock rising edge
10
ns
t
LEW
LE pulse width
50
ns
t
CLE
Clock falling edge to LE rising edge
50
ns
t
LEC
LE falling edge to Clock rising edge
50
ns
t
Data Out
Data Out delay after Clock falling edge (f
o
LD pin)
C
L
= 50 pf
90
ns
Main Divider (Including Prescaler)
f
in
1
Operating frequency
300
1800
MHz
f
in
2
Operating frequency
45
550
MHz
Pf
in
1
Input level range
External AC coupling
-7
5
dBm
Pf
in
2
Input level range
External AC coupling
-10
5
dBm
f
c
Comparison frequency
10
MHz
Reference Divider
f
r
Operating frequency
50
MHz
V
fr
Input sensitivity
External AC coupling (note 1)
0.5
V
P-P
Note 1:
CMOS logic levels may be used if DC coupled.
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