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參數(shù)資料
| 型號(hào)： | PE3293 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis |
| 中文描述： | 1.8GHz/550MHz雙分?jǐn)?shù)N超低的雜散鎖相環(huán)頻率合成 |
| 文件頁(yè)數(shù)： | 10/18頁(yè) |
| 文件大?。?/td> | 266K |
| 代理商： | PE3293 |
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PE3293
Product Specification
Programmable Divide Values
(R1, R2, F1, F2, A1, A2, M1, M2)
Copyright
Peregrine Semiconductor Corp. 2003
Page 10 of 18
File No. 70/0015~02C
|
UTSi
CMOS RFIC SOLUTIONS
Data is clocked into the 21-bit shift register, MSB
first. When LE is asserted HIGH, data is latched
into the registers addressed by the last two bits
shifted into the 21-bit register, according to Table 8.
For example, to program the PLL1 (RF) swallow
counter, A
1
, the last two bits shifted into the register
(S
0
, S
1
) would be (1,1). The 5-bit A
1
counter would
then be programmed according to Table 9. For
normal operation, S
16
of address (0,0) (the Test bit)
must be programmed to 0 even if PLL2 (IF) is not
used.
Table 9. PE3293 Counter Programming Example
Divide Value
MSB
LSB
Address
S
11
S
10
S
9
S
8
S
7
S
1
S
0
A
14
A
13
A
12
A
11
A
10
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
2
0
0
0
1
0
1
1
-
-
-
-
-
-
1
1
31
1
1
1
1
1
1
1
Program Modes
Several modes of operation can be programmed with bits C
10
- C
14
and C
20
- C
24
, including the phase detector
polarity, charge pump high impedance, output of the f
o
LD pin and power-down modes. The PE3293 modes of
operation are shown on Table 10. The truth table for the f
o
LD output is shown in Table 11.
Table 10. PE3293 Program Modes
S
15
S
14
S
13
S
12
S
11
S
1
S
0
C
24
See Table 11
C
23
See Table 11
C
22
0 = PLL1 CP normal
1 = PLL1 CP High Z
C
21
(Note 2)
0 = PLL2 Phase Detector inverted
1 = PLL2 Phase Detector normal
C
20
(Note 1)
0 = PLL2 on
1 = PLL2 off
0
0
C
14
See Table 11
C
13
See Table 11
C
12
0 = PLL1 CP normal
1 = PLL1 CP High Z
C
11
(Note 2)
0 = PLL1 Phase Detector inverted
1 = PLL1 Phase Detector normal
C
10
(Note 1)
0 = PLL1 on
1 = PLL1 off
1
0
Note 1:
The PLL1 power-down mode disables all of PLL1’s components except the R
1
counter and the reference frequency input
buffer, with CP1 (pin 3) and f
in
1 (pin 5) becoming high impedance. The power down of PLL2 has similar results with CP2 (pin 18)
and f
in
2 (pin 16) becoming high impedance. Power down of both PLL1 and PLL2 further disables counters R
1
and R
2
, the reference
frequency input, and the f
o
LD output, causing f
r
(pin 8) and f
o
LD (pin 10) to become high impedance. The Serial Control Interface
remains active at all times.
Note 2:
The C
11
and C
21
bits should be set according to the voltage versus frequency slope of the VCO as shown in Figure 7. This
relationship presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted.
Figure 6. VCO Characteristics
When VCO1 (RF) slope is positive like (1), C
11
should be set HIGH.
When VCO1 (RF) slope is negative like (2), C
11
should be set LOW.
When VCO2 (IF) slope is positive like (1), C
21
should be set HIGH.
When VCO2 (IF) slope is negative like (2), C
21
should be set LOW.
VCO
Output
Frequency
(1) Positive slope VCO
(2) Negative slope VCO
VCO Input voltage
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