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參數(shù)資料
| 型號： | PE3293 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis |
| 中文描述： | 1.8GHz/550MHz雙分數(shù)N超低的雜散鎖相環(huán)頻率合成 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 266K |
| 代理商： | PE3293 |
PE3293
Product Specification
Figure 2. Pin Configuration: TSSOP (JEDEC MO-153-AC)
Copyright
Peregrine Semiconductor Corp. 2003
Page 2 of 18
File No. 70/0015~02C
|
UTSi
CMOS RFIC SOLUTIONS
Table 1. Pin Descriptions
Pin No.
Pin Name
Type
Description
1
N / C
No connect.
2
V
DD
(Note 1)
Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed as
close as possible to this pin and be connected directly to the ground plane.
3
CP1
Output
Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external VCO.
4
GND
Ground.
5
f
in
1
Input
Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.8 GHz.
6
Dec1
Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane.
7
V
DD1
PLL1 prescaler power supply. 3.3 kohm resistor to V
DD
.
8
f
r
Input
Reference frequency input.
9
GND
Ground.
10
f
o
LD
Output
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and data
out of the shift register. CMOS output (see Table 11, f
o
LD Programming Truth Table).
11
Clock
Input
CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift
register.
12
Data
Input
Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.
13
LE
Input
Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into
one of the four appropriate latches (as assigned by the control bits).
14
V
DD2
Output
PLL2 prescaler power supply. 3.3 kohm resistor to V
DD
.
15
Dec2
Output
Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane.
16
f
in
2
Input
Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550 MHz.
17
GND
Ground.
18
CP2
Output
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external VCO.
19
V
DD
(Note 1)
Same as pin 2.
20
V
DD
(Note 1)
Same as pin 2.
Note 1:
V
DD
pins 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.
N/C
1
V
DD
2
CP1
3
GND
4
f
in
1
5
Dec1
6
V
DD
1
7
f
r
8
GND
9
f
o
LD
10
Clock
11
Data
12
LE
13
V
DD
2
14
DEC2
15
f
in
2
16
GND
17
CP2
18
V
DD
19
V
DD
20
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